XC2VP70 Xilinx, Inc., XC2VP70 Datasheet - Page 106

• Manufacturer Part Number: XC2VP70
• Description: Virtex-ii Pro Field Programmable Gate Array
• Manufacturer: Xilinx, Inc.

Table 57: Sample Window
Table 58: Pin-to-Pin Setup/Hold: Source-Synchronous Configuration
DS083-3 (v2.12) November 11, 2003
Advance Product Specification
Notes:
1. This parameter indicates the total sampling error of Virtex-II Pro DDR input registers across voltage, temperature, and process. The
Notes:
1. IFF = Input Flip-Flop
2. The timing values were measured using the fine-phase adjustment feature of the DCM.
3. The worst-case duty-cycle distortion and DCM jitter on CLK0 and CLK180 is included in these measurements.
Sampling Error at Receiver Pins
Data Input Set-Up and Hold Times Relative to a
Forwarded Clock Input Pin, Using DCM and
Global Clock Buffer.
For situations where clock and data inputs
conform to different standards, adjust the setup
and hold values accordingly using the values
shown in IOB Input Switching Characteristics
Standard
No Delay
Global Clock and IFF with DCM
characterization methodology uses the DCM to capture the DDR input registers’ edges of operation. These measurements include:
- CLK0 and CLK180 DCM jitter
- Worst-case Duty-Cycle Distortion - T
- DCM accuracy (phase offset)
- DCM phase shift resolution.
These measurements do not include package or clock tree skew.
Adjustments, page
Description
R
Description
22.
(1)
DCD_CLK180
Symbol
T
SAMP
T
PSDCM_0
Virtex-II Pro™ Platform FPGAs: DC and Switching Characteristics
Symbol
www.xilinx.com
1-800-255-7778
/T
PHDCM_0
XC2VP100
XC2VP125
XC2VP20
XC2VP30
XC2VP40
XC2VP50
XC2VP70
XC2VP2
XC2VP4
XC2VP7
Device
XC2VP100
XC2VP125
XC2VP20
XC2VP30
XC2VP40
XC2VP50
XC2VP70
XC2VP2
XC2VP4
XC2VP7
Device
–
7
–
7
Speed Grade
Speed Grade
0.50
0.50
0.50
0.50
0.50
0.50
–
6
–
6
0.50
0.50
0.50
0.50
0.50
0.50
–
–
5
5
Units
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
49