XC2VP70 Xilinx, Inc., XC2VP70 Datasheet - Page 2

• Manufacturer Part Number: XC2VP70
• Description: Virtex-ii Pro Field Programmable Gate Array
• Manufacturer: Xilinx, Inc.

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DS083-1 (v2.4.2) August 25, 2003
Summary of Virtex-II Pro Features
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•
Table 1: Virtex-II Pro FPGA Family Members
RocketIO Transceiver Features
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•
•
•
•
•
DS083-1 (v2.4.2) August 25, 2003
Advance Product Specification
Notes:
1. Logic Cell = (1) 4-input LUT + (1)FF + Carry Logic
2. These devices can be ordered in a configuration without RocketIO transceivers. See
XC2VP2
XC2VP4
XC2VP7
XC2VP20
XC2VP30
XC2VP40
XC2VP50
XC2VP70
XC2VP100
XC2VP125
Device
High-Performance Platform FPGA Solution, Including
-
-
Based on Virtex™-II Platform FPGA Technology
-
-
-
Full-Duplex Serial Transceiver (SERDES) Capable of
Baud Rates from 600 Mb/s to 3.125 Gb/s
120 Gb/s Duplex Data Rate (24 Channels)
Monolithic Clock Synthesis and Clock Recovery (CDR)
Fibre Channel, 10G Fibre Channel, Gigabit Ethernet,
10 Gb Attachment Unit Interface (XAUI), and
Infiniband-Compliant Transceivers
8-, 16-, or 32-bit Selectable Internal FPGA Interface
8B /10B Encoder and Decoder (optional)
© 2003 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm.
Up to twenty-four RocketIO™ embedded
multi-gigabit transceivers
Up to four IBM
Flexible logic resources
SRAM-based in-system configuration
Active Interconnect technology
All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.
0
Transceiver
(2)
RocketIO
0
0
0
16 or 20
Blocks
(2)
(2)
(2)
, 20, or 24
4
4
8
8
8
or 12
or 16
or 20
®
PowerPC
Processor
PowerPC
Blocks
R
0
1
2
2
1
2
2
2
2
4
®
RISC processor blocks
125,136
Cells
11,088
20,880
74,448
30,816
43,632
53,136
99,216
Logic
3,168
6,768
(1)
CLB (1 = 4 slices =
13,696
19,392
23,616
33,088
44,096
55,616
Slices
1,408
3,008
4,928
9,280
0
0
www.xilinx.com
max 128 bits)
1-800-255-7778
8
0
RAM (Kb)
Max Distr
1,034
1,378
1,738
154
290
428
606
738
Virtex-II Pro™ Platform FPGAs:
Introduction and Overview
Advance Product Specification
Virtex-II Pro family members and resources are shown in
Table
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•
•
•
•
•
•
•
44
94
-
-
-
-
-
50Ω /75Ω on-chip Selectable Transmit and Receive
Terminations
Programmable Comma Detection
Channel Bonding Support (from 2 to 24 Channels)
Rate Matching via Insertion/Deletion Characters
Four Levels of Selectable Pre-Emphasis
Five Levels of Output Differential Voltage
Per-Channel Internal Loopback Modes
2.5V Transceiver Supply Voltage
1.
SelectRAM™+ memory hierarchy
Dedicated 18-bit x 18-bit multiplier blocks
High-performance clock management circuitry
SelectI/O™-Ultra technology
XCITE Digitally Controlled Impedance (DCI) I/O
18 X 18 Bit
Multiplier
Blocks
136
192
232
328
444
556
12
28
44
88
Table 3
Blocks
Block SelectRAM+
18 Kb
136
192
232
328
444
556
12
28
44
88
for package configurations.
Max Block
RAM (Kb)
10,008
1,584
2,448
3,456
4,176
5,904
7,992
216
504
792
DCMs
12
12
4
4
4
8
8
8
8
8
Maximum
I/O Pads
1,164
1,200
User
204
348
396
564
644
804
852
996
1