XC2VP70 Xilinx, Inc., XC2VP70 Datasheet - Page 23

• Manufacturer Part Number: XC2VP70
• Description: Virtex-ii Pro Field Programmable Gate Array
• Manufacturer: Xilinx, Inc.

Functional Description: FPGA
Table 4: Supported Differential Signal I/O Standards
Table 5: Supported DCI I/O Standards
14
Notes:
1.
2.
Notes:
1.
2.
3.
4. N/R = no requirement.
LDT_25
LVDS_25
LVDSEXT_25
BLVDS_25
ULVDS_25
LVPECL_25
LDT_25_DT
LVDS_25_DT
LVDSEXT_25_DT
ULVDS_25_DT
LVDCI_33
LVDCI_25
LVDCI_DV2_25
LVDCI_18
LVDCI_DV2_18
LVDCI_15
LVDCI_DV2_15
GTL_DCI
GTLP_DCI
HSTL_I_DCI
HSTL_II_DCI
HSTL_III_DCI
HSTL_IV_DCI
HSTL_I_DCI_18
HSTL_II_DCI_18
HSTL_III_DCI_18
HSTL_IV_DCI_18
SSTL2_I_DCI
SSTL2_II_DCI
SSTL18_I_DCI
SSTL18_II_DCI
LVDS_25_DCI
LVDSEXT_25_DCI
These standards support on-chip 100Ω termination.
N/R = no requirement.
LVDCI_XX is LVCMOS output controlled impedance buffers,
matching all or half of the reference resistors.
These are SSTL compatible.
SSTL18_I is not a JEDEC-supported standard.
Standard
Standard
I/O
I/O
(1)
(1)
(1)
(1)
(2)
(2)
(3)
(1)
Output
V
Output
2.5
2.5
2.5
2.5
2.5
2.5
2.5
2.5
2.5
2.5
CCO
V
3.3
2.5
2.5
1.8
1.8
1.5
1.5
1.2
1.5
1.5
1.5
1.5
1.5
1.8
1.8
1.8
1.8
2.5
2.5
1.8
1.8
2.5
2.5
CCO
Input
V
N/R
N/R
N/R
N/R
N/R
N/R
2.5
2.5
2.5
2.5
CCO
Input
V
3.3
2.5
2.5
1.8
1.8
1.5
1.5
1.2
1.5
1.5
1.5
1.5
1.5
1.8
1.8
1.8
1.8
2.5
2.5
1.8
1.8
2.5
2.5
CCO
Input
V
N/R
N/R
N/R
N/R
N/R
N/R
N/R
N/R
N/R
N/R
REF
Input
V
0.75
0.75
1.25
1.25
N/R
N/R
N/R
N/R
N/R
N/R
N/R
N/R
N/R
0.8
1.0
0.9
0.9
0.9
0.9
1.1
1.1
0.9
0.9
REF
0.500 – 0.740
0.330 – 0.700
0.250 – 0.450
0.500 – 0.740
0.345 – 1.185
0.500 – 0.740
0.247 – 0.454
0.330 – 0.700
0.500 – 0.740
0.247 – 0.454
Termination
Output
V
Series
Series
Series
Series
Series
Series
Series
Single
Single
Single
Single
Single
Single
Type
Split
Split
Split
Split
Split
Split
Split
Split
Split
Split
OD
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1-800-255-7778
Logic Resources
IOB blocks include six storage elements, as shown in
Figure
Each storage element can be configured either as an
edge-triggered D-type flip-flop or as a level-sensitive latch.
On the input, output, and 3-state path, one or two DDR reg-
isters can be used.
Double data rate is directly accomplished by the two regis-
ters on each path, clocked by the rising edges (or falling
edges) from two different clock nets. The two clock signals
are generated by the DCM and must be 180 degrees out of
phase, as shown in
and 3-state data signals, each being alternately clocked out.
10.
OCK2
OCK2
OCK1
OCK1
Reg
Reg
Reg
Reg
Figure 10: Virtex-II Pro IOB Block
DDR mux
DDR mux
3-State
Output
Figure
11. There are two input, output,
DS083-2 (v2.9) October 14, 2003
Advance Product Specification
IOB
ICK1
ICK2
Reg
Reg
Input
PAD
DS031_29_100900
R