XC2VP70 Xilinx, Inc., XC2VP70 Datasheet - Page 115

• Manufacturer Part Number: XC2VP70
• Description: Virtex-ii Pro Field Programmable Gate Array
• Manufacturer: Xilinx, Inc.

Virtex-II Pro Pin Definitions
Table 4: Virtex-II Pro Pin Definitions (Continued)
4
With /ZZZ:
D0/DIN, D1, D2,
D3, D4, D5, D6,
D7
CS_B
RDWR_B
BUSY/DOUT
INIT_B
GCLKx (S/P)
VRP
VRN
V
Dedicated Pins
CCLK
PROG_B
DONE
M2, M1, M0
HSWAP_EN
TCK
TDI
TDO
TMS
PWRDWN_B
REF
Pin Name
(1)
(unsupported)
Input/Output •
Input/Output These are clock input pins that connect to Global Clock Buffers. These pins become
Input/Output Configuration clock. Output in Master mode or Input in Slave mode.
Input/Output DONE is a bidirectional signal with an optional internal pull-up resistor. As an output,
Bidirectional
(open-drain)
(open-drain)
Direction
Output
Output
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
•
•
•
In SelectMAP mode, this is the active-low Chip Select signal. The pin becomes a user
I/O after configuration, unless the SelectMAP port is retained.
In SelectMAP mode, this is the active-low Write Enable signal. The pin becomes a user
I/O after configuration, unless the SelectMAP port is retained.
When Low, this pin indicates that the configuration memory is being cleared. When held
Low, the start of configuration is delayed. During configuration, a Low on this output
indicates that a configuration data error has occurred. The pin becomes a user I/O after
configuration.
regular user I/Os when not needed for clocks.
This pin is for the DCI voltage reference resistor of P transistor (per bank).
This pin is for the DCI voltage reference resistor of N transistor (per bank).
These are input threshold voltage pins. They become user I/Os when an external
threshold voltage is not needed (per bank).
Active Low asynchronous reset to configuration logic. This pin has a permanent weak
pull-up resistor.
this pin indicates completion of the configuration process. As an input, a Low level on
DONE can be configured to delay the start-up sequence.
Configuration mode selection.
Enable I/O pullups during configuration.
Boundary Scan Clock.
Boundary Scan Data Input.
Boundary Scan Data Output.
Boundary Scan Mode Select.
Active Low power-down pin (unsupported). Driving this pin Low can adversely affect
device operation and configuration. PWRDWN_B is internally pulled High, which is its
default state. It does not require an external pull-up.
In SelectMAP mode, D0 through D7 are configuration data pins. These pins
become user I/Os after configuration, unless the SelectMAP port is retained.
In bit-serial modes, DIN (D0) is the single-data input. This pin becomes a user I/O
after configuration.
In SelectMAP mode, BUSY controls the rate at which configuration data is loaded.
The pin becomes a user I/O after configuration, unless the SelectMAP port is
retained.
In bit-serial modes, DOUT provides preamble and configuration data to
downstream devices in a daisy-chain. The pin becomes a user I/O after
configuration.
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Description
DS083-4 (v2.5.5) August 25, 2003
Advance Product Specification
R