XC2VP70 Xilinx, Inc., XC2VP70 Datasheet - Page 7

• Manufacturer Part Number: XC2VP70
• Description: Virtex-ii Pro Field Programmable Gate Array
• Manufacturer: Xilinx, Inc.

IP Core and Reference Support
IP Core and Reference Support
Intellectual Property is part of the Platform FPGA solution.
In addition to the existing FPGA fabric cores, the list below
shows some of the currently available hardware and soft-
ware intellectual properties
Virtex-II Pro by Xilinx. Each IP core is modular, portable,
Real-Time Operating System (RTOS) independent, and
CoreConnect compatible for ease of design migration.
Refer to
complete list of cores.
Hardware Cores
•
•
•
•
Software Cores
•
•
•
•
•
•
Table 3: Virtex-II Pro Device/Package Combinations and Maximum Number of Available I/Os
6
Notes:
1. The RocketIO transceivers in devices in the FF1148 and FF1696 packages are not bonded out to the package pins.
2. Consult Xilinx for package options supporting 24 RocketIO transceivers.
FG256
FG456
FG676
FF672
FF896
FF1152
FF1148
FF1517
FF1704
FF1696
Pkg
Bus Infrastructure cores (arbiters, bridges, and more)
Memory cores (DDR, Flash, and more)
Peripheral cores (UART, IIC, and more)
Networking cores (ATM, Ethernet, and more)
Boot code
Test code
Device drivers
Protocol stacks
RTOS integration
Customized board support package
www.xilinx.com/ipcenter
Pitch
(mm)
1.00
1.00
1.00
1.00
1.00
1.00
1.00
1.00
1.00
1.00
17 x 17
23 x 23
26 x 26
27 x 27
31 x 31
35 x 35
35 x 35
40 x 40
42.5 x
42.5 x
(mm)
Size
42.5
42.5
XC2VP2 XC2VP4 XC2VP7 XC2VP20 XC2VP30 XC2VP40 XC2VP50 XC2VP70 XC2VP100 XC2VP125
140 / 4
156 / 4
204 / 4
specially
140 / 4
248 / 4
348 / 4
for the latest and most
248 / 8
396 / 8
396 / 8
developed
Available User I/Os / Available RocketIO Transceivers
404 / 8
556 / 8
564 / 8
www.xilinx.com
1-800-255-7778
for
644 / 8
416 / 8
556 / 8
Virtex-II Pro Device/Package
Combinations and Maximum I/Os
Offerings include ball grid array (BGA) packages with
1.0 mm pitch. In addition to traditional wire-bond intercon-
nects, flip-chip interconnect is used in some of the BGA
offerings. The use of flip-chip interconnect offers more I/Os
than are possible in wire-bond versions of the similar pack-
ages. Flip-chip construction offers the combination of high
pin count and excellent power dissipation.
The
(Table
RocketIO transceivers for each device and package using
wire-bond or flip-chip technology.
•
•
The FF1148 and FF1696 packages have no RocketIO
transceivers bonded out. Extra SelectIO-Ultra resources
occupy available pins in these packages, resulting in a
higher user I/O count. FF1148 and FF1696 packages are
available for the XC2VP40, XC2VP50, XC2VP100, and
XC2VP125 devices only.
The I/Os per package count includes all user I/Os except
the 15 control pins (CCLK, DONE, M0, M1, M2, PROG_B,
PWRDWN_B, TCK, TDI, TDO, TMS, HSWAP_EN, DXN,
DXP, and RSVD), VBATT, and RocketIO transceiver pins.
FG denotes Wirebond fine-pitch BGA (1.00 mm pitch).
FF denotes FlipChip fine-pitch BGA (1.00 mm pitch).
Virtex-II Pro
3) details the maximum number of user I/Os and
804 / 0
692 / 12
416 / 8
(1)
812 / 0
692 / 16
852 / 16
device/package
(1)
964 / 16
996 / 20
DS083-1 (v2.4.2) August 25, 2003
Advance Product Specification
1,164 / 0
1,040 / 20
combination
(1)
1,200 / 0
1,040 / 20
table
(1)
R