XC2VP70 Xilinx, Inc., XC2VP70 Datasheet - Page 18

• Manufacturer Part Number: XC2VP70
• Description: Virtex-ii Pro Field Programmable Gate Array
• Manufacturer: Xilinx, Inc.

debuggers with processor control that includes stopping,
starting, and stepping the PPC405 core. These extensions
are compliant with the IEEE 1149.1 specifications for
vendor-specific extensions.
The Trace port provides instruction execution trace informa-
tion to an external trace tool. The PPC405 core is capable of
back trace and forward trace. Back trace is the tracing of
instructions prior to a debug event while forward trace is the
tracing of instructions after a debug event.
The processor JTAG port and the FPGA JTAG port can be
accessed independently, or the two can be programmati-
cally linked together and accessed via the dedicated FPGA
JTAG pins.
For detailed information on the PPC405 JTAG interface,
please refer to the "JTAG Interface" section of the
405 Processor Block Reference Guide
CoreConnect™ Bus Architecture
The Processor Block is compatible with the CoreConnect™
bus architecture. Any CoreConnect compliant cores includ-
ing Xilinx soft IP can integrate with the Processor Block
through this high-performance bus architecture imple-
mented on FPGA fabric.
Functional Description: Embedded PowerPC 405 Core
This section offers a brief overview of the various functional blocks shown in
DS083-2 (v2.9) October 14, 2003
Advance Product Specification
R
PLB Master
PLB Master
Interface
Interface
D-Cache
I-Cache
Array
Array
Cache Units
Instruction
Cache
Cache
Data
Unit
Unit
Controller
Controller
D-Cache
I-Cache
Figure 7: Embedded PPC405 Core Block Diagram
Instruction
OCM
Data
OCM
Instruction Shadow
Data Shadow
Unified TLB
(64 Entry)
PowerPC
MMU
(8 Entry)
(4 Entry)
TLB
TLB
www.xilinx.com
1-800-255-7778
The CoreConnect architecture provides three buses for
interconnecting Processor Blocks, Xilinx soft IP, third party
IP, and custom logic, as shown in
•
•
•
High-performance peripherals connect to the high-band-
width, low-latency PLB. Slower peripheral cores connect to
the OPB, which reduces traffic on the PLB, resulting in
greater overall system performance.
For more information, refer to:
http://www-3.ibm.com/chips/techlib/techlib.nfs/product
families/CoreConnect_Bus_Architecture/
Virtex-II Pro™ Platform FPGAs: Functional Description
Fetch & Decode
Execution Unit (EXU)
Decode
32 x 32
Execution Unit
Fetch
Logic
GPR
and
Processor Local Bus (PLB)
On-Chip Peripheral Bus (OPB)
Device Control Register (DCR) bus
System
Core
ALU
3-Element
Figure 6: CoreConnect Block Diagram
(PFB1,
Queue
PFB0,
Fetch
DCD)
MAC
Processor Local Bus
Figure
Instruction
System
Core
Processor
7.
Block
JTAG
Debug Logic
Watchdog)
Timers
Debug
Data
System
Timers
Core
(FIT,
PIT,
DS083-2_01_062001
&
Instruction
Trace
Bridge
DCR Bus
Bus
DCR
Bus
Figure
CoreConnect Bus Architecture
Peripheral
On-Chip Peripheral Bus
Core
6:
Peripheral
DS083-2_02a_010202
Core
9