XC2VP20-6FF1152C Xilinx, Inc., XC2VP20-6FF1152C Datasheet - Page 70

• Manufacturer Part Number: XC2VP20-6FF1152C
• Description: Pro Platform FPGA
• Manufacturer: Xilinx, Inc.

Virtex-II Pro Switching Characteristics
IOB Input Switching Characteristics
Input delays associated with the pad are specified for LVCMOS 2.5V levels. For other standards, adjust the delays with the
values shown in
Table 26: IOB Input Switching Characteristics
70
Notes:
1.
Propagation Delays
Propagation Delays
Setup and Hold Times With Respect
to Clock at IOB Input Register
Set/Reset Delays
Pad to I output, no delay
Pad to I output, with delay
Pad to output IQ via transparent
latch, no delay
Pad to output IQ via transparent
latch, with delay
Clock CLK to output IQ
Pad, no delay
Pad, with delay
ICE input
SR input (IFF, synchronous)
SR input to IQ (asynchronous)
GSR to output IQ
Input timing for LVCMOS25 is measured at 1.25V. For other I/O standards, see
Description
IOB Input Switching Characteristics Standard Adjustments, page
T
T
T
IOPICKD
IOICECK
IOPICK
T
Symbol
T
T
T
T
T
IOSRCKI
T
T
IOCKIQ
IOSRIQ
IOPLID
GSRQ
IOPID
IOPLI
IOPI
/T
/T
/T
IOICKP
IOICKPD
IOCKICE
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XC2VP20
XC2VP50
XC2VP20
XC2VP50
XC2VP20
XC2VP50
Device
XC2VP2
XC2VP4
XC2VP7
XC2VP2
XC2VP4
XC2VP7
XC2VP2
XC2VP4
XC2VP7
All
All
All
All
All
All
All
All
Table
–8
30.
Speed Grade
71.
–
7
DS083-3 (v1.0) January 31, 2002
Advance Product Specification
–
6
ns, max
ns, max
ns, max
ns, max
ns, max
ns, max
ns, max
ns, max
ns, max
ns, max
ns, max
ns, max
ns, max
ns, max
ns, max
ns, max
ns, max
ns, max
ns, max
ns, max
ns, min
ns, min
ns, min
Units
R