XC2VP20-6FF1152C Xilinx, Inc., XC2VP20-6FF1152C Datasheet - Page 16

• Manufacturer Part Number: XC2VP20-6FF1152C
• Description: Pro Platform FPGA
• Manufacturer: Xilinx, Inc.

Functional Description: Processor Block
Functional Description:
Processor Block
This section briefly describes the interfaces and compo-
nents of the Processor Block. The subsequent section,
Functional Description: PowerPC 405 Core
page
For an in-depth discussion on both Processor Block and
PPC405, refer to the Processor Block Manual and the
PPC405 User Manual.
Processor Block Overview
Figure 5
Block.
Within the Virtex-II Pro Processor Block, there are four com-
ponents:
•
•
•
•
Embedded PowerPC 405 RISC Core
The PowerPC 405D5 core is a 0.13 µm implementation of
the IBM PowerPC 405D4 core. The advanced process tech-
nology enables the embedded PowerPC 405 (PPC405)
core to operate at 300+ MHz while maintaining low power
16
Processor Block = CPU Core + Interface Logic + CPU-FPGA Interface
Embedded IBM PowerPC 405-D5 RISC CPU core
On-Chip Memory (OCM) controllers and interfaces
Clock/control interface logic
CPU-FPGA Interfaces
19, offers a summary of major PPC405 core features.
Figure 5: Processor Block Architecture
shows the internal architecture of the Processor
BRAM
BRAM
BRAM
BRAM
CPU-FPGA Interfaces
PPC 405
Interface Logic
Core
Control
Control
BRAM
BRAM
BRAM
BRAM
beginning on
DS083-2_03a_060701
www.xilinx.com
1-800-255-7778
consumption. Specially designed interface logic integrates
the core with the surrounding CLBs, block RAMs, and gen-
eral routing resources. Up to four Processor Blocks can be
available in a single Virtex-II Pro device.
The PPC405 core implements the PowerPC User Instruc-
tion Set Architecture (UISA), user-level registers, program-
ming model, data types, and addressing modes for 32-bit
fixed-point operations. 64-bit operations, auxiliary proces-
sor operations, and floating-point operations are trapped
and can be emulated in software.
Most of the PPC405 core features are compatible with the
specifications for the PowerPC Virtual Environment
Architecture (VEA) and Operating Environment Architecture
(OEA). They also provide a number of optimizations and
extensions to the lower layers of the PowerPC Architecture.
The full architecture of the PPC405 is defined by the
PowerPC Embedded Environment and the PowerPC UISA.
On-Chip Memory (OCM) Controllers
Introduction
The OCM controllers serve as dedicated interfaces
between the block RAMs in the FPGA fabric (see
Block SelectRAM Resources, page
available on the embedded PPC405 core. The OCM signals
on the PPC405 core are designed to provide very quick
access to a fixed amount of instruction and data memory
space. The OCM controller provides an interface to both the
64-bit Instruction-Side Block RAM (ISBRAM) and the 32-bit
Data-Side Block RAM (DSBRAM). The designer can
choose to implement:
•
•
•
•
One of OCM’s primary advantages is that it guarantees a
fixed latency of execution for a higher level of determinism.
Additionally, it reduces cache pollution and thrashing, since
the cache remains available for caching code from other
memory resources.
Typical applications for DSOCM include scratch-pad mem-
ory, as well as use of the dual-port feature of block RAM to
enable bidirectional data transfer between processor and
FPGA. Typical applications for ISOCM include storage of
interrupt service routines.
Functional Features
Common Features
•
•
•
ISBRAM only
DSBRAM only
Both ISBRAM and DSBRAM
No ISBRAM and no DSBRAM
Separate Instruction and Data memory interface
between Processor core and BRAMs in FPGA
Dedicated interface to Device Control Register (DCR)
bus for ISOCM and DSOCM
Single-cycle and multi-cycle mode option for I-side and
D-side interfaces
DS083-2 (v1.0) January 31, 2002
Advance Product Specification
39) and OCM signals
18 Kb
R