XC2VP20-6FF1152C Xilinx, Inc., XC2VP20-6FF1152C Datasheet - Page 33

• Manufacturer Part Number: XC2VP20-6FF1152C
• Description: Pro Platform FPGA
• Manufacturer: Xilinx, Inc.

For single-port configurations, distributed SelectRAM mem-
ory has one address port for synchronous writes and asyn-
chronous reads.
For dual-port configurations, distributed SelectRAM mem-
ory has one port for synchronous writes and asynchronous
reads and another port for asynchronous reads. The func-
tion generator (LUT) has separated read address inputs
(A1, A2, A3, A4) and write address inputs (WG1/WF1,
WG2/WF2, WG3/WF3, WG4/WF4).
In single-port mode, read and write addresses share the
same address bus. In dual-port mode, one function genera-
tor (R/W port) is connected with shared read and write
addresses. The second function generator has the A inputs
(read) connected to the second read-only port address and
the W inputs (write) shared with the first read/write port
address.
Figure
ple configurations.
DS083-2 (v1.0) January 31, 2002
Advance Product Specification
WCLK
A[3:0]
A[4]
WE
WCLK
Figure 24: Distributed SelectRAM (RAM16x1S)
D
A[3:0]
Figure 25: Single-Port Distributed SelectRAM
WE
24,
D
(BX)
(BY)
(SR)
Figure
4
(BY)
(SR)
R
4
4
4
RAM 16x1S
WE
CK
A[4:1]
WG[4:1]
WSG
25, and
WS
RAM 32x1S
WE0
WE
CK
G[4:1]
WG[4:1]
F[4:1]
WF[4:1]
WSF
RAM
WS
WS
WSG
RAM
RAM
(RAM32x1S)
DI
DI
DI
Figure 26
D
D
D
F5MUX
(optional)
illustrate various exam-
D
Q
(optional)
D
DS031_02_100900
Q
Output
Registered
Output
DS083-2_10_050901
Output
Registered
Output
www.xilinx.com
1-800-255-7778
Similar to the RAM configuration, each function generator
(LUT) can implement a 16 x 1-bit ROM. Five configurations
are
ROM128x1, and ROM256x1. The ROM elements are cas-
cadable to implement wider or/and deeper ROM. ROM con-
tents are loaded at configuration.
number of LUTs occupied by each configuration.
Table 11: ROM Configuration
Shift Registers
Each function generator can also be configured as a 16-bit
shift register. The write operation is synchronous with a
clock input (CLK) and an optional clock enable, as shown in
Figure
4-bit address bus, A[3:0]. The configurable 16-bit shift regis-
Virtex-II Pro™ Platform FPGAs: Functional Description
DPRA[3:0]
Figure 26: Dual-Port Distributed SelectRAM
available:
27. A dynamic read access is performed through the
WCLK
A[3:0]
A[3:0]
WE
128 x 1
256 x 1
D
16 x 1
32 x 1
64 x 1
ROM
(SR)
(BY)
4
ROM16x1,
4
4
(RAM16x1D)
RAM 16x1D
WE
CK
WE
CK
G[4:1]
WG[4:1]
WSG
G[4:1]
WG[4:1]
WSG
WS
WS
dual_port
RAM
dual_port
RAM
ROM32x1,
DI
DI
Number of LUTs
D
D
Table 11
16 (2 CLBs)
8 (1 CLB)
DS031_04_110100
1
2
4
shows the
ROM64x1,
SPO
DPO
33