XC2VP20-6FF1152C Xilinx, Inc., XC2VP20-6FF1152C Datasheet - Page 3

• Manufacturer Part Number: XC2VP20-6FF1152C
• Description: Pro Platform FPGA
• Manufacturer: Xilinx, Inc.

Architecture
Virtex-II Pro Array Overview
Virtex-II Pro devices are user-programmable gate arrays
with various configurable elements and embedded cores
optimized for high-density and high-performance system
designs. Virtex-II Pro devices implement the following func-
tionality:
•
•
•
•
•
•
•
A new generation of programmable routing resources called
Active Interconnect Technology interconnects all of these
elements. The general routing matrix (GRM) is an array of
routing switches. Each programmable element is tied to a
switch matrix, allowing multiple connections to the general
routing matrix. The overall programmable interconnection is
hierarchical and designed to support high-speed designs.
All
resources, are controlled by values stored in static memory
cells. These values are loaded in the memory cells during
configuration and can be reloaded to change the functions
of the programmable elements.
Virtex-II Pro Features
This section briefly describes Virtex-II Pro features.
Rocket I/O Multi-Gigabit Transceiver Cores
The Rocket I/O Multi-Gigabit Transceiver core, based on
Mindspeed’s SkyRail technology, is a flexible paral-
lel-to-serial and serial-to-parallel transceiver embedded
core used for high-bandwidth interconnection between
buses, backplanes, or other subsystems.
Multiple user instantiations in an FPGA are possible, provid-
ing up to 80 Gb/s of full-duplex raw data transfer. Each
DS083-1 (v1.0) January 31, 2002
Advance Product Specification
Embedded high-speed serial transceivers enable data
bit rate up to 3.125 Gb/s per channel.
Embedded IBM PowerPC 405 RISC CPU cores
provide performance of 300+ MHz.
SelectI/O-Ultra blocks provide the interface between
package pins and the internal configurable logic. Most
popular and leading-edge I/O standards are supported
by the programmable IOBs.
Configurable Logic Blocks (CLBs) provide functional
elements for combinatorial and synchronous logic,
including basic storage elements. BUFTs (3-state
buffers) associated with each CLB element drive
dedicated segmentable horizontal routing resources.
Block SelectRAM memory modules provide large
18 Kb storage elements of True Dual-Port RAM.
Embedded multiplier blocks are 18-bit x 18-bit
dedicated multipliers.
Digital Clock Manager (DCM) blocks provide
self-calibrating, fully digital solutions for clock
distribution delay compensation, clock multiplication
and division, and coarse- and fine-grained clock phase
shifting.
programmable
R
elements,
including
the
routing
www.xilinx.com
1-800-255-7778
Virtex-II Pro™ Platform FPGAs: Introduction and Overview
channel can be operated at a maximum data transfer rate of
3.125 Gb/s.
Each Rocket I/O core implements the following functional-
ity:
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
PowerPC 405 Processor Block
The PPC405 RISC CPU can execute instructions at a sus-
tained rate of one instruction per cycle. On-chip instruction
and data cache reduce design complexity and improve sys-
tem throughput.
The PPC405 features include:
•
•
Serializer and deserializer (SERDES)
Monolithic clock synthesis and clock recovery (CDR)
Fibre Channel, Gigabit Ethernet, XAUI, and Infiniband
compliant transceivers
8-, 16-, or 32-bit selectable FPGA interface
8B/10B encoder and decoder with bypassing option on
each channel
Channel bonding support (two to sixteen channels)
-
Receiver clock recovery tolerance of up to
75 non-transitioning bits
50 /75 on-chip selectable TX and RX terminations
Programmable comma detection
Rate matching via insertion/deletion characters
Automatic lock-to-reference function
Optional TX and RX data inversion
Four levels of pre-emphasis support
Per-channel serial and parallel transmitter-to-receiver
internal loopback modes
Cyclic Redundancy Check (CRC) support
PowerPC RISC CPU
-
-
-
-
-
-
-
-
Storage Control
-
-
-
Elastic buffers for inter-chip deskewing and
channel-to-channel alignment
Implements the PowerPC User Instruction Set
Architecture (UISA) and extensions for embedded
applications
Thirty-two 32-bit general purpose registers (GPRs)
Static branch prediction
Five-stage pipeline with single-cycle execution of
most instructions, including loads/stores
Unaligned and aligned load/store support to cache,
main memory, and on-chip memory
Hardware multiply/divide for faster integer
arithmetic (4-cycle multiply, 35-cycle divide)
Enhanced string and multiple-word handling
Big/little endian operation support
Separate instruction and data cache units, both
two-way set-associative and non-blocking
Eight words (32 bytes) per cache line
16 KB array Instruction Cache Unit (ICU), 16 KB
array Data Cache Unit (DCU)
3