XC2VP20-6FF1152C Xilinx, Inc., XC2VP20-6FF1152C Datasheet - Page 47

• Manufacturer Part Number: XC2VP20-6FF1152C
• Description: Pro Platform FPGA
• Manufacturer: Xilinx, Inc.

Two separate components of the phase shift range must be
understood:
•
•
The
equation:
The full range of this attribute is always -255 to +255, but its
practical range varies with CLKIN frequency, as constrained
by the
the total delay achievable by the phase shift delay line. Total
delay is a function of the number of delay taps used in the
circuit. Across process, voltage, and temperature, this abso-
lute range is guaranteed to be as specified under
ing
Absolute range (fixed mode) = ±
Absolute range (variable mode) = ±
The reason for the difference between fixed and variable
modes is as follows. For variable mode to allow symmetric,
dynamic sweeps from -255/256 to +255/256, the DCM sets
the "zero phase skew" point as the middle of the delay line,
Table 24: DCM Frequency Ranges
DS083-2 (v1.0) January 31, 2002
Advance Product Specification
CLK0, CLK180
CLK90, CLK270
CLK2X, CLK2X180
CLKDV
CLKFX, CLKFX180
PHASE_SHIFT
FINE_SHIFT_RANGE
Phase Shift (ns) = (
Parameters.
PHASE_SHIFT
Output Clock
FINE_SHIFT_RANGE
R
CLKOUT_PHASE_SHIFT
= NONE
CLKOUT_PHASE_SHIFT
= FIXED
CLKOUT_PHASE_SHIFT
= VARIABLE
attribute range
attribute is the numerator in the following
PHASE_SHIFT
DCM timing parameter range
CLKIN_FREQ_DLL_LF
CLKIN_FREQ_DLL_LF
CLKIN_FREQ_DLL_LF
CLKIN_FREQ_DLL_LF
CLKIN_FREQ_FX_LF
component, which represents
CLKIN Input
CLKIN
CLKFB
CLKIN
CLKFB
CLKIN
CLKFB
FINE_SHIFT_RANGE
FINE_SHIFT_RANGE
Low-Frequency Mode
/256) * PERIOD
Figure 51: Fine-Phase Shifting Effects
(PS/256) x PERIOD CLKIN
DCM Tim-
CLKOUT_FREQ_1X_LF
CLKOUT_FREQ_1X_LF
CLKOUT_FREQ_2X_LF
CLKOUT_FREQ_DV_LF
CLKOUT_FREQ_FX_LF
(PS negative)
(PS/256) x PERIOD CLKIN
CLKIN
www.xilinx.com
CLK Output
1-800-255-7778
(PS negative)
/2
thus dividing the total delay line range in half. In fixed mode,
since the
ration, the entire delay line is available for insertion into
either the CLKIN or CLKFB path (to create either positive or
negative skew).
Taking both of these components into consideration, the fol-
lowing are some usage examples:
•
•
•
Operating Modes
The frequency ranges of DCM input and output clocks
depend
low-frequency mode or high-frequency mode, according to
Table
Characteristics (Module
Virtex-II Pro™ Platform FPGAs: Functional Description
If PERIOD
PHASE_SHIFT in
variable mode it is limited to
If PERIOD
PHASE_SHIFT in
variable mode it is limited to
If PERIOD
PHASE_SHIFT
24. For actual values, see
PHASE_SHIFT
on
(PS/256) x PERIOD CLKIN
CLKIN_FREQ_DLL_HF
CLKIN_FREQ_DLL_HF
CLKIN_FREQ_FX_HF
(PS positive)
(PS/256) x PERIOD CLKIN
CLKIN
CLKIN
CLKIN
CLKIN Input
the
is limited to
(PS positive)
NA
NA
= 2 *
=
fixed mode is limited to
fixed mode is limited to
operating
0.5 *
High-Frequency Mode
FINE_SHIFT_RANGE
value never changes after configu-
FINE_SHIFT_RANGE
FINE_SHIFT_RANGE
3). The CLK2X, CLK2X180,
±
255 in either mode.
±
±
mode
64.
128.
Virtex-II Pro Switching
CLKOUT_FREQ_1X_HF
CLKOUT_FREQ_DV_HF
CLKOUT_FREQ_FX_HF
DS031_48_110300
CLK Output
specified,
, then
±
±
NA
NA
, then
128, and in
255, and in
, then
either
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