XC2VP20-6FF1152C Xilinx, Inc., XC2VP20-6FF1152C Datasheet - Page 12

• Manufacturer Part Number: XC2VP20-6FF1152C
• Description: Pro Platform FPGA
• Manufacturer: Xilinx, Inc.

Functional Description: Rocket I/O Multi-Gigabit Transceiver (MGT)
Clock Synthesizer
Synchronous serial data reception is facilitated by a
clock/data recovery circuit. This circuit uses a fully mono-
lithic Phase Lock Loop (PLL), which does not require any
external components. The clock/data recovery circuit
extracts both phase and frequency from the incoming data
stream. The recovered clock is presented on output
RXRECCLK at 1/20 of the serial received data rate.
The gigabit transceiver multiplies the reference frequency
provided on the reference clock input (REFCLK) by 20. The
multiplication of the clock is achieved by using a fully mono-
lithic PLL that does not require any external components.
No fixed phase relationship is assumed between REFCLK,
RXRECCLK, and/or any other clock that is not tied to either
of these clocks. When the 4-byte or 1-byte receiver data
path is used, RXUSRCLK and RXUSRCLK2 have different
frequencies, and each edge of the slower clock is aligned to
a falling edge of the faster clock. The same relationships
apply to TXUSRCLK and TXUSRCLK2.
Clock and Data Recovery
The clock/data recovery (CDR) circuits will lock to the refer-
ence clock automatically if the data is not present. For
proper operation, the frequency of the reference clock must
be within
It is critical to keep power supply noise low in order to mini-
mize common and differential noise modes into the
clock/data recovery circuitry. Refer to the Rocket I/O User
Guide for more details.
Transmitter
FPGA Transmit Interface
The FPGA can send either one, two, or four characters of
data to the transmitter. Each character can be either 8 bits
or 10 bits wide. If 8-bit data is applied, the additional inputs
become control signals for the 8B/10B encoder. When the
8B/10B encoder is bypassed, the 10-bit character order is
generated as follows:
8B/10B Encoder
A bypassable 8B/10B encoder is included. The encoder
uses the same 256 data characters and 12 control charac-
ters that are used for Gigabit Ethernet, Fibre Channel, and
InfiniBand.
The encoder accepts 8 bits of data along with a K-character
signal for a total of 9 bits per character applied, and
generates a 10 bit character for transmission. If the
K-character signal is High, the data is encoded into one of
the twelve possible K-characters available in the 8B/10B
code. If the K-character input is Low, the 8 bits are encoded
12
TXCHARDISPMODE[0]
TXCHARDISPVAL[0]
TXDATA[7:0]
±
100 ppm of the nominal frequency.
(last bit transmitted is TXDATA[0])
(first bit transmitted)
www.xilinx.com
1-800-255-7778
as standard data. If the K-character input is High, and a
user applies other than one of the twelve possible
combinations, TXKERR indicates the error.
Disparity Control
The 8B/10B encoder is initialized with a negative running
disparity. Unique control allows forcing the current running
disparity state.
TXRUNDISP signals its current running disparity. This may
be useful in those cases where there is a need to manipu-
late the initial running disparity value.
Bits TXCHARDISPMODE and TXCHARDISPVAL control
the generation of running disparity before each byte.
For example, the transceiver can generate the sequence
or
by specifying inverted running disparity for the second and
fourth bytes.
Transmit FIFO
Proper operation of the circuit is only possible if the FPGA
clock (TXUSRCLK) is frequency-locked to the reference
clock (REFCLK). Phase variations up to one clock cycle are
allowable. The FIFO has a depth of four. Overflow or under-
flow conditions are detected and signaled at the interface.
Bypassing of this FIFO is programmable.
Serializer
The multi-gigabit transceiver multiplies the reference fre-
quency provided on the reference clock input (REFCLK) by
20. Clock multiplication is achieved by using a fully mono-
lithic PLL requiring no external components. Data is con-
verted from parallel to serial format and transmitted on the
TXP and TXN differential outputs. Bit 0 is transmitted first
and bit 19 is transmitted last.
The electrical connection of TXP and TXN can be inter-
changed through configuration. This option can be con-
trolled by an input (TXPOLARITY) at the FPGA transmitter
interface. This facilitates recovery from situations where
printed circuit board traces have been reversed.
Transmit Termination
On-chip termination is provided at the transmitter, eliminat-
ing the need for external termination. Programmable
options exist for 50 (default) and 75 termination.
Pre-Emphasis Circuit and Swing Control
Four selectable levels of pre-emphasis (10% [default], 20%,
25%, and 33%) are available. Optimizing this setting allows
the transceiver to drive up to 20 inches of FR4 at the maxi-
mum baud rate.
The programmable output swing control can adjust the dif-
ferential output level between 400 mV and 800 mV in four
increments of 100 mV.
K28.5+ K28.5+ K28.5– K28.5–
K28.5– K28.5– K28.5+ K28.5+
DS083-2 (v1.0) January 31, 2002
Advance Product Specification
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