XC2VP20-6FF1152C Xilinx, Inc., XC2VP20-6FF1152C Datasheet - Page 20

• Manufacturer Part Number: XC2VP20-6FF1152C
• Description: Pro Platform FPGA
• Manufacturer: Xilinx, Inc.

Functional Description: PowerPC 405 Core
operation requested by the CPU is stalled; the DCU auto-
matically increases the priority of the current request to the
PLB.
The DCU provides additional features that allow the pro-
grammer to tailor its performance for a given application.
The DCU can function in write-back or write-through mode,
as controlled by the Data Cache Write-through Register
(DCWR) or the Translation Look-aside Buffer (TLB); the
cache controller can be tuned for a balance of performance
and memory coherency. Write-on-allocate, controlled by the
store word on allocate (SWOA) field of the Core Configura-
tion Register 0 (CCR0), can inhibit line fills caused by store
misses, to further reduce potential pipeline stalls and
unwanted external bus traffic.
Fetch and Decode Logic
The fetch and decode logic maintains a steady flow of
instructions to the execution unit by placing up to two
instructions in the fetch queue. The fetch queue consists of
three buffers: pre-fetch buffer 1 (PFB1), pre-fetch buffer 0
(PFB0) and decode (DCD). The fetch logic ensures that
instructions proceed directly to decode when the queue is
empty.
Static branch prediction as implemented on the PPC405
core takes advantage of some standard statistical proper-
ties of code. Branches with negative address displacement
are by default assumed taken. Branches that do not test the
condition or count registers are also predicted as taken. The
PPC405 core bases branch prediction upon these default
conditions when a branch is not resolved and speculatively
fetches along the predicted path. The default prediction can
be overridden by software at assembly or compile time.
Branches are examined in the decode and pre-fetch buffer 0
fetch queue stages. Two branch instructions can be handled
simultaneously. If the branch in decode is not taken, the
fetch logic fetches along the predicted path of the branch
instruction in pre-fetch buffer 0. If the branch in decode is
taken, the fetch logic ignores the branch instruction in
pre-fetch buffer 0.
Execution Unit
The PPC405 core has a single issue execution unit (EXU),
which contains the register file, arithmetic logic unit (ALU),
and the multiply-accumulate (MAC) unit. The execution unit
performs all 32-bit PowerPC integer instructions in hard-
ware.
The register file is comprised of thirty-two 32-bit general
purpose registers (GPR), which are accessed with three
read ports and two write ports. During the decode stage,
data is read out of the GPRs and fed to the execution unit.
Likewise, during the write-back stage, results are written to
the GPR. The use of the five ports on the register file
enables either a load or a store operation to execute in par-
allel with an ALU operation.
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Memory Management Unit (MMU)
The PPC405 core has a 4 GB address space, which is pre-
sented as a flat address space.
The MMU provides address translation, protection func-
tions, and storage attribute control for embedded applica-
tions. The MMU supports demand-paged virtual memory
and other management schemes that require precise con-
trol of logical-to-physical address mapping and flexible
memory protection. Working with appropriate system-level
software, the MMU provides the following functions:
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The MMU can be disabled under software control. If the
MMU is not used, the PPC405 core provides other storage
control mechanisms.
Translation Look-Aside Buffer (TLB)
The Translation Look-Aside Buffer (TLB) is the hardware
resource that controls translation and protection. It consists
of 64 entries, each specifying a page to be translated. The
TLB is fully associative; a given page entry can be placed
anywhere in the TLB. The translation function of the MMU
occurs pre-cache. Cache tags and indexing use physical
addresses.
Software manages the establishment and replacement of
TLB entries. This gives system software significant flexibility
in implementing a custom page replacement strategy. For
example, to reduce TLB thrashing or translation delays,
software can reserve several TLB entries in the TLB for glo-
bally accessible static mappings. The instruction set pro-
vides several instructions used to manage TLB entries.
These instructions are privileged and require the software
to be executing in supervisor state. Additional TLB instruc-
tions are provided to move TLB entry fields to and from
GPRs.
The MMU divides logical storage into pages. Eight page
sizes (1 KB, 4 KB, 16 KB, 64 KB, 256 KB, 1 MB, 4 MB, and
16 MB) are simultaneously supported, such that, at any
given time, the TLB can contain entries for any combination
of page sizes. In order for a logical to physical translation to
exist, a valid entry for the page containing the logical
address must be in the TLB. Addresses for which no TLB
entry exists cause TLB-Miss exceptions.
To improve performance, four instruction-side and eight
data-side TLB entries are kept in shadow arrays. The
Translation of the 4 GB effective address space into
physical addresses
Independent enabling of instruction and data
translation/protection
Page-level access control using the translation
mechanism
Software control of page replacement strategy
Additional control over protection using zones
Storage attributes for cache policy and speculative
memory access control
DS083-2 (v1.0) January 31, 2002
Advance Product Specification
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