LM3S301 Luminary Micro, Inc, LM3S301 Datasheet - Page 234

• Manufacturer Part Number: LM3S301
• Description: Lm3s301 Arm Microcontroller
• Manufacturer: Luminary Micro, Inc

Universal Asynchronous Receiver/Transmitter (UART)
234
Reset
Reset
Type
Type
UART Data (UARTDR)
Offset 0x000
31:12
RO
RO
31
15
0
0
Bit
10
11
9
Register 1: UART Data (UARTDR), offset 0x000
This register is the data register (the interface to the FIFOs).
When FIFOs are enabled, data written to this location is pushed onto the transmit FIFO. If FIFOs
are disabled, data is stored in the transmitter holding register (the bottom word of the transmit
FIFO). A write to this register initiates a transmission from the UART.
For received data, if the FIFO is enabled, the data byte and the 4-bit status (break, frame, parity
and overrun) is pushed onto the 12-bit wide receive FIFO. If FIFOs are disabled, the data byte and
status are stored in the receiving holding register (the bottom word of the receive FIFO). The
received data can be retrieved by reading this register.
RO
RO
30
14
0
0
reserved
reserved
Name
OE
BE
PE
RO
RO
29
13
0
0
RO
RO
28
12
0
0
Type
RO
RO
RO
RO
OE
RO
RO
27
11
0
0
BE
RO
RO
26
10
0
0
Reset
0
0
0
0
PE
RO
RO
25
0
9
0
Preliminary
Description
Reserved bits return an indeterminate value, and should never
be changed.
UART Overrun Error
1=New data was received when the FIFO was full, resulting in
data loss.
0=There has been no data loss due to a FIFO overrun.
UART Break Error
This bit is set to 1 when a break condition is detected, indicating
that the receive data input was held Low for longer than a full-
word transmission time (defined as start, data, parity, and stop
bits).
In FIFO mode, this error is associated with the character at the
top of the FIFO. When a break occurs, only one 0 character is
loaded into the FIFO. The next character is only enabled after
the received data input goes to a 1 (marking state) and the next
valid start bit is received.
UART Parity Error
This bit is set to 1 when the parity of the received data character
does not match the parity defined by bits 2 and 7 of the
UARTLCRH register.
In FIFO mode, this error is associated with the character at the
top of the FIFO.
FE
RO
RO
24
0
8
0
reserved
R/W
RO
23
0
7
0
R/W
RO
22
0
6
0
R/W
RO
21
0
5
0
R/W
RO
20
0
4
0
DATA
R/W
RO
19
0
3
0
R/W
RO
18
0
2
0
R/W
RO
17
July 5, 2006
0
1
0
R/W
RO
16
0
0
0