LM3S301 Luminary Micro, Inc, LM3S301 Datasheet - Page 207

• Manufacturer Part Number: LM3S301
• Description: Lm3s301 Arm Microcontroller
• Manufacturer: Luminary Micro, Inc

July 5, 2006
Reset
Reset
Type
Type
Bit/Field
ADC Interrupt Status and Clear (ADCISC)
Offset 0x00C
RO
RO
31
15
0
0
31:4
3
2
1
0
Register 4: ADC Interrupt Status and Clear (ADCISC), offset 0x00C
This register provides the mechanism for clearing interrupt conditions, and shows the status of
controller interrupts generated by the Sample Sequencers. When read, each bit field is the logical
AND of the respective INR and MASK bits. Interrupts are cleared by writing a 1 to the
corresponding bit position. If software is polling the ADCRIS instead of generating interrupts, the
INR bits are still cleared via the ADCISC register, even if the IN bit is not set.
RO
RO
30
14
0
0
reserved
Name
IN3
IN2
IN1
IN0
RO
RO
29
13
0
0
RO
RO
28
12
0
0
R/W1C
R/W1C
R/W1C
R/W1C
Type
RO
RO
RO
27
11
0
0
RO
RO
26
10
0
0
reserved
Reset
0
0
0
0
0
RO
RO
25
0
9
0
Preliminary
Description
Reserved bits return an indeterminate value, and should never
be changed.
This bit is set by hardware when the MASK3 and INR3 bits are
both 1, providing a level-based interrupt to the controller. It is
cleared by writing a 1, and also clears the INR3 bit.
This bit is set by hardware when the MASK2 and INR2 bits are
both 1, providing a level based interrupt to the controller. It is
cleared by writing a 1, and also clears the INR2 bit.
This bit is set by hardware when the MASK1 and INR1 bits are
both 1, providing a level based interrupt to the controller. It is
cleared by writing a 1, and also clears the INR1 bit.
This bit is set by hardware when the MASK0 and INR0 bits are
both 1, providing a level based interrupt to the controller. It is
cleared by writing a 1, and also clears the INR0 bit.
RO
RO
24
0
8
0
reserved
RO
RO
23
0
7
0
RO
RO
22
0
6
0
RO
RO
21
0
5
0
RO
RO
20
0
4
0
R/W1C
IN3
RO
19
0
3
0
LM3S301 Data Sheet
R/W1C
IN2
RO
18
0
2
0
R/W1C
IN1
RO
17
0
1
0
R/W1C
IN0
RO
16
0
0
0
207