LM3S301 Luminary Micro, Inc, LM3S301 Datasheet - Page 13

• Manufacturer Part Number: LM3S301
• Description: Lm3s301 Arm Microcontroller
• Manufacturer: Luminary Micro, Inc

Register 4:
Register 5:
Register 6:
Register 7:
Register 8:
Register 9:
Register 10:
Register 11:
Register 12:
Register 13:
Register 14:
Register 15:
Register 16:
Register 17:
Register 18:
Register 19:
Register 20:
Analog-to-Digital Converter (ADC).............................................................................................. 198
Register 1:
Register 2:
Register 3:
Register 4:
Register 5:
Register 6:
Register 7:
Register 8:
Register 9:
Register 10:
Register 11:
Register 12:
Register 13:
Register 14:
Register 15:
Register 16:
Register 17:
Register 18:
Register 19:
Register 20:
Register 21:
Register 22:
Register 23:
Register 24:
Register 25:
Register 26:
Universal Asynchronous Receiver/Transmitter (UART) ........................................................... 227
Register 1:
Register 2:
Register 3:
July 5, 2006
Watchdog Interrupt Clear (WDTICR), offset 0x00C ................................................................ 181
Watchdog Raw Interrupt Status (WDTRIS), offset 0x010 ....................................................... 182
Watchdog Masked Interrupt Status (WDTMIS), offset 0x014.................................................. 183
Watchdog Lock (WDTLOCK), offset 0xC00 ............................................................................ 184
Watchdog Test (WDTTEST), offset 0x418 .............................................................................. 185
Watchdog Peripheral Identification 4 (WDTPeriphID4), offset 0xFD0..................................... 186
Watchdog Peripheral Identification 5 (WDTPeriphID5), offset 0xFD4..................................... 187
Watchdog Peripheral Identification 6 (WDTPeriphID6), offset 0xFD8..................................... 188
Watchdog Peripheral Identification 7 (WDTPeriphID7), offset 0xFDC .................................... 189
Watchdog Peripheral Identification 0 (WDTPeriphID0), offset 0xFE0 ..................................... 190
Watchdog Peripheral Identification 1 (WDTPeriphID1), offset 0xFE4 ..................................... 191
Watchdog Peripheral Identification 2 (WDTPeriphID2), offset 0xFE8 ..................................... 192
Watchdog Peripheral Identification 3 (WDTPeriphID3), offset 0xFEC .................................... 193
Watchdog PrimeCell Identification 0 (WDTPCellID0), offset 0xFF0........................................ 194
Watchdog PrimeCell Identification 1 (WDTPCellID1), offset 0xFF4........................................ 195
Watchdog PrimeCell Identification 2 (WDTPCellID2), offset 0xFF8........................................ 196
Watchdog PrimeCell Identification 3 (WDTPCellID3 ), offset 0xFFC ...................................... 197
ADC Active Sample Sequencer (ADCACTSS), offset 0x000 .................................................. 204
ADC Raw Interrupt Status (ADCRIS), offset 0x004................................................................. 205
ADC Interrupt Mask (ADCIM), offset 0x008 ............................................................................ 206
ADC Interrupt Status and Clear (ADCISC), offset 0x00C........................................................ 207
ADC Overflow Status (ADCOSTAT), offset 0x010 .................................................................. 208
ADC Event Multiplexer Select (ADCEMUX), offset 0x014 ...................................................... 209
ADC Underflow Status (ADCUSTAT), offset 0x018 ................................................................ 210
ADC Sample Sequencer Priority (ADCSSPRI), offset 0x020.................................................. 211
ADC Processor Sample Sequence Initiate (ADCPSSI), offset 0x028 ..................................... 212
ADC Sample Sequence Input Multiplexer Select 0 (ADCSSMUX0), offset 0x040.................. 213
ADC Sample Sequence Control 0 (ADCSSCTL0), offset 0x044............................................. 215
ADC Sample Sequence Result FIFO 0 (ADCSSFIFO0), offset 0x048.................................... 217
ADC Sample Sequence FIFO 0 Status (ADCSSFSTAT0), offset 0x04C................................ 218
ADC Sample Sequence Input Multiplexer Select 1 (ADCSSMUX1), offset 0x060.................. 219
ADC Sample Sequence Control 1 (ADCSSCTL1), offset 0x064............................................. 220
ADC Sample Sequence Result FIFO 1 (ADCSSFIFO1), offset 0x068.................................... 220
ADC Sample Sequence FIFO 1 Status (ADCSSFSTAT1), offset 0x06C................................ 220
ADC Sample Sequence Input Multiplexer Select 2 (ADCSSMUX2), offset 0x080.................. 221
ADC Sample Sequence Control 2 (ADCSSCTL2), offset 0x084............................................. 222
ADC Sample Sequence Result FIFO 2 (ADCSSFIFO2), offset 0x088.................................... 222
ADC Sample Sequence FIFO 2 Status (ADCSSFSTAT2), offset 0x08C................................ 222
ADC Sample Sequence Input Multiplexer Select 3 (ADCSSMUX3), offset 0x0A0 ................. 223
ADC Sample Sequence Control 3 (ADCSSCTL3), offset 0x064............................................. 224
ADC Sample Sequence Result FIFO 3 (ADCSSFIFO3), offset 0x0A8 ................................... 224
ADC Sample Sequence FIFO 3 Status (ADCSSFSTAT3), offset 0x0AC ............................... 224
ADC Test Mode Loopback (ADCTMLB), offset 0x100 ............................................................ 225
UART Data (UARTDR), offset 0x000 ...................................................................................... 234
UART Receive Status/Error Clear (UARTRSR/UARTECR), offset 0x004 .............................. 236
UART Flag (UARTFR), offset 0x018 ....................................................................................... 238
Preliminary
LM3S301 Data Sheet
13