SPC8104 S-MOS Systems, SPC8104 Datasheet - Page 89

• Manufacturer Part Number: SPC8104
• Description: VGA LCD CONTROLLER
• Manufacturer: S-MOS Systems

bit 3
bit 2
bit 0
bit 7
bit 6
bits 5-0
bits 7-0
SPC8104
05 Mode Addressing Select Register RW
n/a
06 LCD Support Register RW
XSCL Enable LP Timing
07 Frame Buffer Start Register RW
bit 7
412-1.0
n/a
Select
bit 6
S-MOS Systems, Inc. • Tel: [phone] • Fax: [phone] • http://www.smos.com
Sequencer CPU Cycles Disable
Setting this bit to 1 prevents the Sequencer from generating DRAM cycles from a CPU R/W
request. Any subsequent memory read cycles will read the contents of the display FIFO. A memory
write with this bit set is an invalid cycle and will have no effect.
3CDh Port Enable
Setting this bit to 1 enables access to the Page Select Register at port 3CDh. Setting this bit to 0
disables access to this register.
Extended Display Page Enable
This bit is used to enable the Extended Display Page function. This function allows the display
memory to wrap into the upper 256K bytes, and for 256K bytes of memory to be displayed starting
anywhere in the entire 512K byte extended display memory space. If this bit is set to 1, then the
extended display page function is enabled. If this bit is set to 0, then the extended display page
function is disabled.
XSCL Enable
This bit is used to adjust the XSCL shift clock output timing. When this bit is set to 0, XSCL is
masked off during the horizontal non-display period. When this bit is set to 1, XSCL is not masked
off during the horizontal non-display period. Refer to section 7.0 on page 24, and the LCD panel
manufacturer’s specification to determine the correct setting of this bit.
LP Timing Select
This bit is used to adjust the LP latch pulse output timing. When this bit is set to 0, the LP latch
pulse falling edge occurs 12 clock periods before the falling edge of the shift clock (XSCL). When
this bit is set to 1, the LP latch pulse falling edge occurs 4 clock periods before the falling edge of
the shift clock. Refer to section 7.0 on page 24, and the LCD panel manufacturer’s specification to
determine the correct setting of this bit.
WF Count Bits [5:0]
These bits are used to adjust the WF output signal period. The binary value stored in these bits
represents the number of LP pulses -1 between toggles of the WF output. A of value of 0 pro-
grammed in these bits causes the WF output to toggle every frame. VAlues of 01h - 3Fh pro-
grammed in these bits result in WF toggling every (1 + n) LP pulses.
Frame Buffer Start Position Bits [7:0]
These bits store the 8 most significant bits of the 18-bit start address location for the frame buffer.
The lower 10 bits of the frame buffer start address are always 0.
n/a
bit 5
bit 5
n/a
bit 4
bit 4
Frame Buffer Start Position
X15-SP-001-08.1
n/a
bit 3
bit 3
WF Count
Sequencer
CPU Cycles
Disable
bit 2
bit 2
Hardware Functional Specification
3CDh Port
Enable
bit 1
bit 1
Extended
Display
Page Enable
bit 0
bit 0
SP1-63