SPC8104 S-MOS Systems, SPC8104 Datasheet - Page 75

• Manufacturer Part Number: SPC8104
• Description: VGA LCD CONTROLLER
• Manufacturer: S-MOS Systems

Active State
Power Down State
Doze Mode 2
This power save mode has an Active State and a Power Down State. When there are no CPU to
display memory access, the chip enters the Power Down State. In the Power Down State, the
internal clock rate is reduced. Any display memory read or write request by the CPU returns the
chip to the Active State to service the memory access. After the memory access is completed,
the chip returns to the Power Down State.
Active State
Power Down State
Software Suspend Mode
SPC8104
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412-1.0
Functionally the same as normal operation.
Absence of display memory and I/O writes for a long period puts the chip into the Power Down State.
Static display with black and white only gray shades.
RAM type LCD driver in self-refresh mode.
Various internal blocks not required for display refresh are shut down.
Display memory and I/O read and write allowed, but display memory or I/O write returns the chip to the
Active State.
Functionally the same as normal operation.
Completion or absence of memory read/write cycle puts the chip into the Power Down State.
Internal clock is slowed down by a selectable factor from 2 to 8, while maintaining DRAM refresh rate.
Static display with reduced frame rate.
I/O read and write allowed.
Display memory read or write request by the CPU returns the chip to the Active State.
No video display accesses to display memory.
No CPU accesses to/from display memory.
Sequencer is halted.
Display memory refresh is maintained and is generated from one of 3 selectable sources: 1) from the active
CLKI input, 2) from the PDCLK pin (32 kHz 50% duty cycle), 3) or from a 64kHz clock source with short
active low pulses connected to pin MEMEN (typically -REFRESH of the ISA bus).
Refresh rate generated can be selected as either 64 kHz or 8 kHz, (for 256 cycle/4 msec, or 256 cycle/32
msec DRAM, respectively).
I/O read/write of all registers is allowed (except LUT registers).
LCDPWR# signal forced high.
LCD interface output signals tri-stated or forced low, depending on the state of the MD[5] configuration pin
during chip reset.
S-MOS Systems, Inc. • Tel: [phone] • Fax: [phone] • http://www.smos.com
X15-SP-001-08.1
Hardware Functional Specification
SP1-49