SPC8104 S-MOS Systems, SPC8104 Datasheet - Page 76

• Manufacturer Part Number: SPC8104
• Description: VGA LCD CONTROLLER
• Manufacturer: S-MOS Systems

Options
Hardware Suspend Mode
Options
Hardware Functional Specification
SP1-50
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Select MEMEN input pin, PDCLK input pin, or internally divided down CLKI as the clock source for display
memory refresh generation.
Select self-refresh mode, for DRAMs that support self-refresh.
CLKI can be masked off if it is not used for DRAM refresh.
No video display accesses to display memory.
No CPU accesses to/from display memory.
Sequencer is halted.
Display memory refresh is maintained and is generated from one of 3 selectable sources: 1) from the active
CLKI input, 2) from the PDCLK pin (32 kHz 50% duty cycle), 3) or from a 64kHz clock source with short
active low pulses connected to pin MEMEN (typically -REFRESH of the ISA bus).
Refresh rate generated can be selected as either 64 kHz or 8 kHz, (for 256 cycle/4 msec, or 256 cycle/32
msec DRAM, respectively).
No I/O register or memory accesses allowed (including LUT).
LCDPWR# signal forced high.
LCD interface output signals tri-stated or forced low, depending on the state of the MD[5] configuration pin
during chip reset.
Most CPU interface input signals are internally masked off (i.e. ignored). All CPU interface output signals are
inactive (except MEMEN).
CLKI will automatically masked off if it is not used for DRAM refresh.
Select MEMEN input pin, PDCLK input pin, or internally divided down CLKI as the clock source for display
memory refresh generation.
Select self-refresh mode, for DRAMs that support self-refresh.
S-MOS Systems, Inc. • Tel: [phone] • Fax: [phone] • http://www.smos.com
X15-SP-001-08.1
412-1.0
SPC8104