SPC8104 S-MOS Systems, SPC8104 Datasheet - Page 13

• Manufacturer Part Number: SPC8104
• Description: VGA LCD CONTROLLER
• Manufacturer: S-MOS Systems

Bus Interface
The Bus Interface is a bridge by which the chip
communicates with the CPU bus. It supports a
16-bit ISA bus.
Port Decoder
The Port Decoder decodes CPU-bus I/O cycles to pro-
vide enable and write strobes for the on-chip I/O regis-
ters.
Memory Decoder
The Memory Decoder monitors the CPU-bus activity and
decodes cycles for the display DRAM. It supplies mem-
ory access control signals to the Sequencer.
Display Memory Address Generator
The Address Generator takes the display and refresh
addresses from the CRT Controller and converts them
into RAS and CAS addresses for the display DRAM, and
multiplexes these display accesses with CPU memory
accesses.
Sequencer
The Sequencer generates internal signals to synchro-
nize the operation of the chip as well as the signals to
control the timing of the display DRAM. The Sequencer
also arbitrates between CPU and video display accesses
to the DRAM. It contains registers that allows selection of
character font set, control the structure of the video
memory and allow write masking of the individual plane
of memory.
Display Memory Interface
The Display Memory Interface is a bridge by which the
chip communicates with the DRAM. It contains buffers
that are used to store recently fetched DRAM data.
Power Save
The Power Save block contains the logic to implement
three software and hardware controlled power down
modes.
Clock Generator/Divider
The Clock Generation contains clock dividing circuits
used by the Power Save block.
SPC8104
FUNCTIONAL BLOCK DESCRIPTION
412-1.0
S-MOS Systems, Inc. • Tel: [phone] • Fax: [phone] • http://www.smos.com
Auxiliary Ports
The Auxiliary Ports are I/O registers used to control func-
tions of the chip beyond the basic VGA register set. Reg-
isters are included for controlling the LCD interface
circuits as well as the power save modes.
CRT Controller
The CRT Controller generates the horizontal and vertical
synchronization signals for the single panel or dual panel
LCD display and character and/or pixel addresses for
display data from DRAM.
Graphics Controller
The Graphics Controller supplies display memory data to
the Attributes Controller during display time and provides
data translation between the CPU bus and the display
memory during CPU read or write access cycles.
VGA Ports
The VGA Ports contain the Miscellaneous Output Status
register and the Video Subsystem Enable register used
in VGA mode.
Attributes Controller
The Attributes Controller takes in pixel and attribute infor-
mation from the Graphics Controller and display DRAM
and formats the data into pixel information which then
passes through the lookup table. It also controls display
character attributes such as blink, underline and horizon-
tal pixel panning.
Look-Up Table
The Lookup Table consists of a memory array of 64 loca-
tions of 4 bits each and hardware to convert VGA palette
writes to gray-scale values.
LCD/MIM Panel Interface
The LCD Interface block converts the display video data
from the Lookup Table into LCD display data. It also gen-
erates control signals necessary to drive single or dual-
panel LCD panels and MIM panels. For monochrome
LCD panels, the LCD interface block generates a maxi-
mum 16 gray shades through frame rate modulation and
dithering techniques.
Data Sheet
DS-7