SPC8104 S-MOS Systems, SPC8104 Datasheet - Page 19

• Manufacturer Part Number: SPC8104
• Description: VGA LCD CONTROLLER
• Manufacturer: S-MOS Systems

Test Function
LCD Panel Interface
SPC8104
Pin Name
TSTCO
TSTEN
N/C
Pin Name
YD
LP
XSCL
UD[0:3]
LD[0:3]
LCDPWR#
WF
412-1.0
Type
I
I
Type
O
O
O
O
O
O
O
S-MOS Systems, Inc. • Tel: [phone] • Fax: [phone] • http://www.smos.com
Pin #
38
82
78
Pin #
25
26
23
34~37
28~31
27
24
Drv
CD
CD
Description
Vertical Scanning Start Pulse output. A logic 1 on this signal, sampled by the LCD/
MIM panel module on the falling edge of LP, is used by the panel row drivers (Y
drivers) to indicate the start of the vertical frame.
Latch Pulse output. The falling edge of this signal is used to latch a row of display
data in the LCD/MIM panel module’s column driver shift registers and to turn on the
row driver (Y driver) for that line.
Shift Clock for LCD panel data or Pixel Clock for MIM panel data. Display data is
clocked out of the chip on the rising edge of this signal, to be shifted into the LCD/
MIM panel module column drivers (X drivers) on each falling edge.
Upper panel display data for dual LCD panel mode. For single LCD panel mode,
these bits are the most significant 4 bits of the 8 bit output data to the panel
(PD[4:7]). For 4-bit single LCD panel mode, these bits are the 4 bits of output data
to the panel. For 4-bit MIM panel mode, these bits are driven 0.
Lower panel display data for dual LCD panel mode. For 8-bit single LCD panel
mode, these bits are the least significant 4 bits of the 8 bit output data to the panel
(PD[0:3]). For 4-bit single LCD panels, these bits are driven 0. For 4-bit MIM panel
mode, these are the 4 bits of output data to the panel.
LCD power control. In normal operation this signal is driven low to enable an
external LCD power supply. This signal is driven high when the chip is put into any
power save mode, or if the Sequencer is in a reset state. It can be used externally
to turn off the panel supply voltage and backlight. After a RESET, this signal is held
high until the CRTC is programmed and running.
LCD Panel Backplane Bias Signal or MIM Panel Data Enable Signal. In LCD panel
mode, the WF signal toggles once per vertical frame period. In MIM panel mode,
this signal goes high whenever display data are valid.
Description
This pin enables the chip’s test mode for the core logic. This pin must
always be unconnected or tied to ground.
This pin enables the chip’s test mode for the I/O cells. This pin must
always be unconnected or tied to ground.
No Connection
Data Sheet
DS-13