SPC8104 S-MOS Systems, SPC8104 Datasheet - Page 87

• Manufacturer Part Number: SPC8104
• Description: VGA LCD CONTROLLER
• Manufacturer: S-MOS Systems

bit 6
bit 5
bit 4
bits 3-2
bit 0
SPC8104
412-1.0
S-MOS Systems, Inc. • Tel: [phone] • Fax: [phone] • http://www.smos.com
MIM Panel Select
When the MIM Panel Select bit is set to 1, MIM panel display hardware is enabled. When this bit is
set to 0, LCD panel display hardware is enabled.
Single/Dual Panel
The Single/Dual Panel bit is used to configure the chip timing for the correct LCD panel type. When
this bit is 0, dual panel mode is enabled. When this bit is 1, single panel mode is enabled.
4/8 Bit Panel Interface
The 4/8 Bit Panel Interface bit configures the LCD output data for either 4 bit or 8 bit single panels.
When this bit is set to 0, an 8 bit single panel interface is provided, with 8 bit pixel data output on
UD[3:0] (msbits) and on LD[3:0] (lsbits). When this bit is set to 1, then a 4 bit single panel interface
is provided, where 4 bit pixel data is output only on UD[3:0]. Note that this bit must be set to 0 for all
dual panel modes.
Suspend Mode Refresh Clock Source Select Bits [1:0]
These bits are used to select the clock source used to generate DRAM refresh in Suspend mode
as follows
CLKI
When this option is selected, the pixel clock input (CLKI) is used as the clock source for DRAM
refresh in Suspend mode.
MEMEN
When this option is selected, the MEMEN input is used as the clock source for DRAM refresh in
Suspend mode. See note 1 of section 10.3 on page 52, for details
Self Refresh
This option may only be used when the DRAMs installed are capable of self-refresh. When this
option is selected, during Suspend mode, the DRAM control lines are driven in such a manner to
cause the DRAM to enter self-refresh mode. When not in self-refresh mode, then CAS-before-RAS
refresh cycles are used during Suspend mode. Note that regardless of the setting of these bits,
CAS-before-RAS refresh cycles are used during Active mode and Doze modes.
PDCLK
When this option is selected, the PDCLK input pin is used as the clock source for DRAM refresh in
Suspend mode. This input should be a 32kHz, 50% duty cycle clock. See note 2 of section 10.3 on
page 52, for details.
32/4 msec Refresh Select
The 32/4msc Refresh Select bit is used to select 256 cycle/4 msec or 256 cycle/32msec DRAM
refresh timing in all modes of operation. When this bit is 0, then 4 msec refresh timing is generated.
When this bit is 1, then 32msec refresh timing is generated. In active mode and Doze modes, this 4
or 32 msec refresh timing is generated from CLKI. In Suspend mode, this 4 or 32 msec refresh tim-
ing is generated from CLKI, from MEMEN input, or the PDCLK input, as selected by AUX[02] bits
3,2.
Suspend Refresh
Clock Source
Select Bit 1
0
0
1
1
Suspend Refresh
Clock Source
Select Bit 0
0
1
0
1
X15-SP-001-08.1
DRAM Refresh Clock
Source in Suspend
Self Refresh
MEMEN
PDCLK
Mode
CLKI
Hardware Functional Specification
SP1-61