AN2692 Freescale Semiconductor / Motorola, AN2692 Datasheet - Page 7

• Manufacturer Part Number: AN2692
• Description: MC9S12NE64 Integrated Ethernet Controller
• Manufacturer: Freescale Semiconductor / Motorola

MC9S12NE64 Packages
The MC9S12NE64 is available in two packages:
The 80-pin TQFP-EP package does not have access to the multiplex address and data bus, and it has
an exposed flag for heat dissipation that requires PCB layout accommodation. If the port pins are not
bonded out in the chosen package, the user must initialize the registers to be inputs with enabled pull-up
resistance to avoid excess current consumption.
shown in bold are not available on the 80-pin package.
Freescale Semiconductor
3.3V
3.3V
•
•
10
10
10
11
11
11
12
12
12
13
13
13
14
14
14
15
15
15
16
16
16
17
17
17
18
18
18
19
19
19
20
20
20
1
1
1
2
2
2
3
3
3
4
4
4
5
5
5
6
6
6
7
7
7
8
8
8
9
9
9
112-pin LQFP package — 70 I/O port pins and 10 input-only pins
80-pin TQFP-EP package — 38 I/O port pins and 10 input-only pins
MII_TXER/KWH6/PH6
MII_TXER/KWH6/PH6
MII_TXER/KWH6/PH6
MII_TXEN/KWH5/PH5
MII_TXEN/KWH5/PH5
MII_TXEN/KWH5/PH5
MII_TXCLK/KWH4/PH4
MII_TXCLK/KWH4/PH4
MII_TXCLK/KWH4/PH4
MII_TXD3/KWH3/PH3
MII_TXD3/KWH3/PH3
MII_TXD3/KWH3/PH3
MII_TXD2/KWH2/PH2
MII_TXD2/KWH2/PH2
MII_TXD2/KWH2/PH2
MII_TXD1/KWH1/PH1
MII_TXD1/KWH1/PH1
MII_TXD1/KWH1/PH1
MII_TXD0/KWH0/PH0
MII_TXD0/KWH0/PH0
MII_TXD0/KWH0/PH0
MII_MDC/KWJ0/PJ0
MII_MDC/KWJ0/PJ0
MII_MDC/KWJ0/PJ0
MII_MDIO/KWJ1/PJ1
MII_MDIO/KWJ1/PJ1
MII_MDIO/KWJ1/PJ1
VDDX1
VDDX1
VDDX1
VSSX1
VSSX1
VSSX1
MII_CRS/KWJ2/PJ2
MII_CRS/KWJ2/PJ2
MII_CRS/KWJ2/PJ2
MII_COL/KWJ3/PJ3
MII_COL/KWJ3/PJ3
MII_COL/KWJ3/PJ3
MII_RXD0/KWG0/PG0
MII_RXD0/KWG0/PG0
MII_RXD0/KWG0/PG0
MII_RXD1/KWG1/PG1
MII_RXD1/KWG1/PG1
MII_RXD1/KWG1/PG1
MII_RXD2/KWG2/PG2
MII_RXD2/KWG2/PG2
MII_RXD2/KWG2/PG2
MII_RXD3/KWG3/PG3
MII_RXD3/KWG3/PG3
MII_RXD3/KWG3/PG3
MII_RXCLK/KWG4/PG4
MII_RXCLK/KWG4/PG4
MII_RXCLK/KWG4/PG4
MII_RXDV/KWG5/PG5
MII_RXDV/KWG5/PG5
MII_RXDV/KWG5/PG5
MII_RXER/KWG6/PG6
MII_RXER/KWG6/PG6
MII_RXER/KWG6/PG6
U1
U1
U1
To configure the bus clock to 25 MHz with a 25-MHz clock input, the CRG
(clock and reset generator) must be configured so that the PLL setting
yields the 25-MHz internal bus clock setting. See the
section for details.
Figure 5. MC9S12NE64 Minimum Web Server Circuit Implementation
C1
C1
C1
0.22
0.22
0.22
MC9S12NE64
MC9S12NE64
MC9S12NE64 Integrated Ethernet Controller, Rev. 0.2
470Pf
470Pf
C10
C10
3.3V
3.3V
3.3V
3.3V
0.22
0.22
0.22
C7
C7
C7
R11
R11
2.2k
2.2k
4700Pf
4700Pf
C11
C11
15pF
15pF
15pF
C8
C8
C8
Y1
Y1
Y1
25 MHz
25 MHz
25 MHz
R10
R10
R10
10M
10M
10M
Figure 6
C9
C9
C9
15pF
15pF
15pF
PHY_VDDRX
PHY_VDDRX
PHY_VDDRX
PL3/DUPLED
PL3/DUPLED
PL3/DUPLED
BKGD/MODC
BKGD/MODC
BKGD/MODC
PL0/ACTLED
PL0/ACTLED
PL0/ACTLED
PL1/LNKLED
PL1/LNKLED
PL1/LNKLED
PL2/SPDLED
PL2/SPDLED
PL2/SPDLED
PHY_VSSRX
PHY_VSSRX
PHY_VSSRX
PHY_VDDTX
PHY_VDDTX
PHY_VDDTX
PL4/COLLED
PL4/COLLED
PL4/COLLED
PHY_VSSTX
PHY_VSSTX
PHY_VSSTX
PHY_RBIAS
PHY_RBIAS
PHY_RBIAS
PHY_VDDA
PHY_VDDA
PHY_VDDA
PHY_VSSA
PHY_VSSA
PHY_VSSA
PHY_RXN
PHY_RXN
PHY_RXN
PHY_RXP
PHY_RXP
PHY_RXP
PHY_TXN
PHY_TXN
PHY_TXN
PHY_TXP
PHY_TXP
PHY_TXP
VDDR
VDDR
VDDR
VDD2
VDD2
VDD2
VSS2
VSS2
VSS2
60
60
60
59
59
59
58
58
58
57
57
57
56
56
56
55
55
55
54
54
54
53
53
53
52
52
52
51
51
51
50
50
50
49
49
49
48
48
48
47
47
47
46
46
46
45
45
45
44
44
44
43
43
43
42
42
42
41
41
41
BACKGROUND DEBUG
BACKGROUND DEBUG
shows the 112-pin LQFP package. Signals
12.4k 1%
12.4k 1%
C4
C4
R5
R5
1
1
3
3
5
5
C3
C3
1
1
3
3
5
5
PL0/ACTLED
PL0/ACTLED
3.3V
3.3V
0.22
0.22
PL4/COLLED
PL4/COLLED
J1
J1
PL1/LNKLED
PL1/LNKLED
PL2/SPDLED
PL2/SPDLED
PL3/DUPLED
PL3/DUPLED
C5
C5
2
2
4
4
6
6
C6
C6
C6
0.22
0.22
2
2
4
4
6
6
0.22
0.22
0.22
0.22
0.22
MC9S12NE64 Integrated Ethernet Controller
3.3V
3.3V
Configuring the CRG
*RESET
*RESET
0.01
0.01
C2
C2
R1
R1
49.9
49.9
49.9
49.9
R3
R3
3.3V
3.3V
R2
R2
R4
R4
49.9
49.9
49.9
49.9
PL3/DUPLED
PL3/DUPLED
PL3/DUPLED
PL2/SPDLED
PL2/SPDLED
PL2/SPDLED
PL4/COLLED
PL4/COLLED
PL1/LNKLED
PL1/LNKLED
PL1/LNKLED
PL0/ACTLED
PL0/ACTLED
EARTH/CHASSIS
EARTH/CHASSIS
T1
T1
T1
6
6
6
5
5
5
4
4
4
3
3
3
2
2
2
1
1
1
8
8
8
OPTIONAL STATUS LED's
OPTIONAL STATUS LED's
MCU SIDE
MCU SIDE
MCU SIDE
R-
R-
R-
CT
CT
CT
R+
R+
R+
T-
T-
T-
CT
CT
CT
T+
T+
T+
.
.
.
TRANSFORMER / RJ-45 CONNECTOR
TRANSFORMER / RJ-45 CONNECTOR
TRANSFORMER / RJ-45 CONNECTOR
LED1
LED1
LNK_LED
LNK_LED
LED2
LED2
LED2
SPD_LED
SPD_LED
SPD_LED
LED3
LED3
DUP_LED
DUP_LED
LED4
LED4
ACT_LED
ACT_LED
LED5
LED5
COL_LED
COL_LED
75 OHMS
75 OHMS
75 OHMS
75 OHMS
75 OHMS
75 OHMS
CABLE SIDE
CABLE SIDE
CABLE SIDE
1000 pF
1000 pF
1000 pF
2kV
2kV
2kV
R7
R7
R6
R6
R6
220
220
220
R8
R8
R8
220
220
220
220
220
R9
R9
220
220
R12
R12
220
220
J6
J6
J6
J7
J7
J7
J8
J8
J8
J3
J3
J3
J2
J2
J2
J4
J4
J4
J5
J5
J5
J1
J1
J1
3.3V
3.3V
6
6
6
7
7
7
8
8
8
3
3
3
2
2
2
4
4
4
5
5
5
1
1
1
RJ-45
RJ-45
7