AN2692 Freescale Semiconductor / Motorola, AN2692 Datasheet - Page 26

• Manufacturer Part Number: AN2692
• Description: MC9S12NE64 Integrated Ethernet Controller
• Manufacturer: Freescale Semiconductor / Motorola

MC9S12NE64 Ethernet Media Access Controller (EMAC)
The MDCSEL bit field sets the MDC frequency and must be equal-to or less-than 2.5 MHz, according to
the IEEE 802.3 specification. Using the following equation, with a 25-MHz clock driving the
MC9S12NE64, the MDCSEL bit field should be set to 0x05:
Other important data registers referenced for MII management read and write operations are included in
the list below with a brief description:
Read Operation
Before performing a read operation by MII management, values for the PADDR and RADDR fields must
be configured by the user indicating which PHY device is to be addressed and which 16-bit register is to
be read, respectively. Setting the OP field in the MCMST register to 0x02 while the BUSY bit is clear
initiates the MII management read and sets the BUSY bit. As soon as the read MII management frame
operation is complete, the BUSY bit clears, the MRDATA register is updated with the MII read result, and
the MMCIF bit is set.
Write Operation
To perform a write operation by MII management interface, the user must provide a value for the PADDR
and RADDR fields, indicating which PHY device is to be addressed and which 16-bit register is to be read,
respectively. The user must also provide the value to be written and store that value in the WDATA data
field. Setting the OP field in the MCMST register to 0x01 while the BUSY bit is clear initiates the MII
management write and sets the BUSY bit. As soon as the write MII management frame operation is
complete, the BUSY bit clears and the MMCIF bit is set.
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MII management PHY address (MPADR) — 5-bit PADDR field in MPADR specifies the PHY
address. When using the MII management interface with the internal PHY, the PHY address setting
in the EMAC and EPHY must match. With a 5-bit field, an MII management interface can target up
to 32 attached PHY devices.
MII management register address (MRADR) — 5-bit RADDR field in MRADR specifies 1 of the 32
internal PHY registers of a device. These internal PHY registers are 16 bits wide. A subset of 32
registers is defined by the IEEE 802.3 standard. These 32 PHY registers can be accessed only
through the MII management interface and are not visible through the MC9S12NE64 register map.
MII management write data (MWDATA) — The 16-bit WDATA data field in MWDATA is used
during an MII management write operation. Before initiating an MII write operation, the value to be
written must be stored in the WDATA data field.
MII management read data (MRDATA) — 16-bit RDATA data field in MRDATA contains the MII
management read operation result. RDATA is valid only when the MII management transfer
complete interrupt flag (MMCIF) in the interrupt event (IEVENT) register is set after a valid read
frame operation.
MDC frequency = bus clock frequency ÷ (2 × MDCSEL)
MC9S12NE64 Integrated Ethernet Controller, Rev. 0.2
Freescale Semiconductor