AN2692 Freescale Semiconductor / Motorola, AN2692 Datasheet - Page 25

• Manufacturer Part Number: AN2692
• Description: MC9S12NE64 Integrated Ethernet Controller
• Manufacturer: Freescale Semiconductor / Motorola

Hardware Generated Pause Control Frame Transmission
If no transmission is in progress and the EMAC is in full-duplex mode, a PAUSE command can be
launched by writing a value of 0x02 to the 2-bit transmit command (TCMD) field in the transmit control
and status (TXCTS) register.
Before transmitting a pause packet, the user must configure the pause timer value and counter (PTIME)
register. The PTIME register specifies the duration of the pause event in units of 512 bit times. To write
to the PTIME register, the pause timer register control (PTRC) bit in the TXCTS register must be set,
because when set, writes to the PTIME register update the duration of a pause control frame.
MII Management Interface
The MII management interface consists of a pair of signals that are used to send and receive information
across the MII between the MAC and PHY to display PHY status information or configure different PHY
options. These signals are also available in external PHY mode (see
management interface, the management clock rate select (MDCSEL) bit field in the MII management
command and status (MCMST) register must be configured. See the MCMST register in
Freescale Semiconductor
The reception of a pause frame stops transmission using the START
command, but it does not prevent transmission of pause control frames. In
addition, pause frames may be accepted even if both receive buffers are
full.
Figure 18. MII Management Command and Status (MCMST) Register
Figure 17. Transmit Control and Status (TXCTS) Register
Reset:
Reset:
Read:
Read:
Write:
Write:
MC9S12NE64 Integrated Ethernet Controller, Rev. 0.2
Figure 17
TXACT
Bit 7
Bit 7
0
0
0
shows the TXCTS register.
OP
= Unimplemented
= Unimplemented
6
0
0
6
0
0
NOTE
BUSY
CSFL
5
0
5
0
MC9S12NE64 Ethernet Media Access Controller (EMAC)
NOPRE
PTRC
4
0
4
0
Table
SSB
3
0
3
0
1). To initialize the MII
2
0
0
2
0
MDCSEL
Figure
1
0
0
1
0
TCMD
18.
Bit 0
Bit 0
0
0
0
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