AN2692 Freescale Semiconductor / Motorola, AN2692 Datasheet - Page 11

• Manufacturer Part Number: AN2692
• Description: MC9S12NE64 Integrated Ethernet Controller
• Manufacturer: Freescale Semiconductor / Motorola

The FLASH uses the PRDIV8 and FDIV[5:0] bits in the FCLKDIV register to divide the oscillator clock
down to the required clock range. PRDIV8 is a 1-bit prescaler value that, if set, divides the oscillator clock
by 8. If PRDIV8 is clear, the oscillator clock is directly fed into the FCLKDIV divider. The FCLKDIV divider
includes a 6-bit value (bits FDIV[5:0]) that generates a divisor from 1 to 64. The divisor is equal-to
(FDIV[5:0]+1). Equation 5 is the resulting equation for the FLASH clock frequency (f
SCI Clock Baud Rate (BR
The bus clock is the input for the SCI modules. Two asynchronous SCIs are available on the
MC9S12NE64. The SCI module version 3.x can be configured to operate in compliance with the IrDA SIR
(IrDA) specification.
The SCI uses the SCIxBDH and SCIxBDL. These registers together provide a 13-bit field for SCI baud
rate (BR
SBR[12:0] can be set to any value from 0 to 8191. When SBR[12:0] = 0, the SCI baud rate generator is
disabled, which reduces system current consumption. For all other SCI baud rate calculations, use
Equation 6.
The MC9S12NE64 SCI also can be operated in IrDA mode. In this mode, the SCI can modulate and
demodulate narrow pulse-widths as defined by the IrDA SIR standard. IrDA mode is enabled by setting
the IREN bit of the SCIBDH register. Equation 6 shows that the BR
bit.
SPI Clock Baud Rate
The synchronous serial peripheral interface (SPI) allows duplex, synchronous serial communication
between the MCU and peripheral devices. The only clock source for the SPI module is the bus clock.
SPI baud rate (BR
3-bit values that contribute to an SPI baud rate divisor, SPPR[2:0] and SPR[2:0]. The first 3-bit value,
identified by the SPPR[2:0] bits, can have a value ranging from 1 to 8. The second 3-bit value, identified
by the SPR[2:0] bits, can have a value ranging from 2 to 256. The mathematical expression of the SPI
baud rate divisor is [(SPPR[2:0]+1) × 2
formula for the SPI baud rate:
Freescale Semiconductor
Equation 5:
Equation 6:
Equation 7:
SCI
) configuration. SBR[12:0] is used to represent the 13-bit SCI baud rate register value.
SPI
) can be set using the SPI control register 2 (SPCR2). The SPCR2 register has two
SCI
BR
MC9S12NE64 Integrated Ethernet Controller, Rev. 0.2
)
f
FLASHCLK
If IREN = 1, BR
SPI
If IREN = 0, BR
=
(SPR[2:0]+1)
[(SPPR[2:0]+1) × 2
=
(8
PRDIV8
SCIIR
SCI
]. Applying this expression to the bus clock yields a
=
=
f
× (FDIV[5:0]+1))
Bus
(16 × SBR[12:0])
f
Bus
(32 × SBR[12:1])
(SPR[2:0]+1)
f
Bus
f
Bus
MC9S12NE64 Integrated Ethernet Controller
SCIIR
]
calculation depends on the IREN
FLASHCLK
).
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