AN2692 Freescale Semiconductor / Motorola, AN2692 Datasheet - Page 29

• Manufacturer Part Number: AN2692
• Description: MC9S12NE64 Integrated Ethernet Controller
• Manufacturer: Freescale Semiconductor / Motorola

Before enabling the EPHY, it is important to configure several EPHY options. Some basic settings will be
made using the EPHYCTL0 and EPHYCTL1 registers, but the majority of the EPHY settings will be
configured through the MII management interface through the EMAC (see the
Status Registers
Configuring the EPHY address, EPHY clock generation disable, and LED enable is straightforward. The
EPHY address must be recorded by the user so that when an MII management operation is executed, the
correct PHY address (see the MPADDR register description in the
provided. The EPHY enable, EPHY clock generation disable, and LED enable bits are typically set or
cleared as part of the EPHY initialization sequence.
Auto-Negotiation Disable
Auto-negotiation is a mechanism that allows two network devices to select the best common speed and
duplex mode automatically during link initiation. The EPHY can be configured to advertise specific speed,
duplex mode, and pause operation abilities by configuring the EPHY auto-negotiate advertisement
register, which is accessible only through the MII management interface (see the
Advertisement Register
The MC9S12NE64 can be operated with or without enabling auto-negotiation. In some instances, the
user may need to specify speed, duplex mode, and flow control settings for a particular application.
Disabling auto-negotiation may be required to establish a link due to interoperability issues.
If the ANDIS bit in the EPHYCTL0 register has a reset value of 1 (and EPHYEN is set, which indicates
that the EPHY is enabled), auto-negotiation is disabled. The ANDIS bit is internally latched to the ANE bit
of the EPHY PHY control register. Typically, the PHY control register is accessible only by the EMAC
through the MII management interface. The PHY control register is part of the internal EPHY register that
Freescale Semiconductor
•
•
•
•
•
•
Register Name
Transceiver Control
Transceiver Control
Ethernet Physical
Ethernet Physical
EPHY address configuration (see EPHYADD[4:0] in EPHYCTL1)
EPHY clock generation disable (see DIS100 and DIS10 in EPHYCTL0)
EPHY LED enable (see LEDEN in EPHYCTL0)
EPHY enable (see EPHYEN in EPHYCTL0)
Auto-negotiation disable setting (see ANDIS in EPHYCTL0)
EPHY interrupt enable (see EPHYIEN in EPHYCTL0)
(EPHYCTL0)
(EPHYCTL1)
Register 0
Register 1
Figure 20. Ethernet Physical Transceiver Control Register 0 and Register 1
section). The EPHY options that can be set through the EPHY register map are:
Reset:
Reset:
Read:
Read:
Write:
Write:
section). Auto-negotiation is defined in the IEEE 802.3 standard in clause 28.
EPHYEN
MC9S12NE64 Integrated Ethernet Controller, Rev. 0.2
Bit 7
0
0
0
= Unimplemented
ANDIS
6
1
0
0
DIS100
5
1
0
0
PHYADD
DIS10
4
1
4
0
MC9S12NE64 Ethernet Physical Transceiver (EPHY)
PHYADD
LEDEN
3
0
3
0
MII Management Interface
EPHYWA
PHYADD
2
0
2
0
I
Internal EPHY Control and
PHYADD
Auto-Negotiate
1
0
0
1
0
EPHYIEN
PHYADD
Bit 0
0
0
0
section) is
29