AN2692 Freescale Semiconductor / Motorola, AN2692 Datasheet - Page 24

• Manufacturer Part Number: AN2692
• Description: MC9S12NE64 Integrated Ethernet Controller
• Manufacturer: Freescale Semiconductor / Motorola

MC9S12NE64 Ethernet Media Access Controller (EMAC)
Because the maximum size of an Ethernet frame is approximately 1.5K, a setting of BUFMAP = 4 would
allow each of the three MC9S12NE64 buffers to hold one Ethernet packet of the maximum allowable size
as dictated by the IEEE 802.3 specification. Setting BUFMAP < 4 can:
The setting of BUFMAP is a system/network design decision. If the devices on a network should accept
only Ethernet packets of a certain size limit, BUFMAP can be configured to ignore packets that are too
large. Setting BUFMAP to create a buffer based on size can reduce the burden on the CPU by ignoring
packets that are too large. It is recommended that the system/network is designed to avoid use of large
packets to maximize user RAM.
If a packet exceeds the receive buffer size, when BUFMAP < 4, the corresponding receive overrun error
flag is set and the packet is filtered-out and ignored. No receive error flag or any other flag is set. No CPU
bandwidth is used because the EMAC state machine does all packet filtering.
Receive Maximum Frame Length (MAXFL)
The receive maximum frame length (MAXFL) bits in the BUFCFG register allow the user to define a
packet size limit. This setting compliments the BUFMAP bits configuration and can also be used to filter-
out unwanted Ethernet packets based on their size. The MAXFL setting specifies the maximum receive
frame length (in bytes). Received Ethernet packets that exceed MAXFL cause the babbling receive error
interrupt flag (BREIF) to set. A CPU interrupt can be configured to occur if the babbling receive error
interrupt enable bit (BREIE) is set.
Setting MAXFL prevents the buffer overrun flag from being set and does not automatically filter-out and
ignore the packets. The packet must be manually removed by clearing the corresponding received valid
flag and clearing the BREIF bit.
Flow Control
Flow control is an optional part of the IEEE 802.3 specification and is applicable only in full-duplex mode.
Flow control allows a network device to pause network traffic by sending or receiving a pause Ethernet
packet to relieve network traffic congestion.
Receiving Pause Frames
If the reception flow control enable (RFCE) bit is set in the RXCTS register, the receiver detects incoming
pause frames. The detection of a pause packet is accomplished by one or both of the following:
A 16-bit value in the incoming pause packet specifies the duration of the pause event in units of 512 bit
times (valid values are from 0x0000 to 0xFFFF). When RFCE is set and a pause frame is detected, the
receive flow control interrupt flag (RFCIF) in the IEVENT register is asserted and the EMAC transmitter
stops transmitting data frames for the received pause duration.
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Maximize user RAM
Filter Ethernet packets based on size
Multicast destination address of 01-80-C2-00-00-01 is detected
Type/length field Ethertype value is 0x8808
MC9S12NE64 Integrated Ethernet Controller, Rev. 0.2
Freescale Semiconductor