AN2692 Freescale Semiconductor / Motorola, AN2692 Datasheet - Page 31

• Manufacturer Part Number: AN2692
• Description: MC9S12NE64 Integrated Ethernet Controller
• Manufacturer: Freescale Semiconductor / Motorola

PHY Control Register
The PHY control register has several important control registers for EPHY basic operation. Some basic
control settings are discussed in this section.
PHY Status Register and Proprietary Status Register
There are two status registers available to the user, the PHY status register and the proprietary status
register. Most status indication, for basic operation, that will be discussed is contained in the proprietary
status register. Typically, the MC9S12NE64 reads this status register when an EPHY interrupt occurs.
The two most important interrupts are those which occur when:
This section describes several important bits. See the MC9S12NE64 data sheet for a complete
description of all bits.
Freescale Semiconductor
•
•
•
•
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Reset:
Reset:
Read:
Read:
Write:
Write:
DATA_RATE — Allows the user to select 10 Mbps or 100 Mbps speed if auto-negotiation is
disabled. If DATA_RATE = 0, then 10 Mbps is selected. If DATA_RATE = 1, then 100 Mbps is
selected.
ANE — Setting this bit enables auto-negotiation. This bit can be latched on start-up based on the
setting of the ANDIS bit in the EPHYCTL0 register (see the
Options
RAN — Setting RAN can restart auto-negotiation. Restarting auto-negotiation is required when the
link to the network is lost. (For example, unplugging the PHY from the network will cause link loss.)
The status of the link can be determined by EPHY interrupts (see the
section).
DPLX — The duplex mode is manually configured with the DPLX bit when auto-negotiation is
disabled. Duplex mode options are full-duplex and half-duplex. Setting the DPLX bit configures the
link for full-duplex mode.
Auto-negotiation is complete
Status of the link has changed
RESET
100-T4
15
15
0
0
section).
LOOP
BACK
100X-
14
14
FD
0
0
Figure 22. PHY Control Register (MII Management Register 0)
Figure 23. PHY Status Register (MII Management Register 1)
DATA
RATE
100X-
HD
13
13
1
1
ANE
10T
MC9S12NE64 Integrated Ethernet Controller, Rev. 0.2
12
12
FD
X
X
PDWN
HDO
11
11
1T
0
0
ISOL
10
10
0
0
0
Figure 22
RAN
9
0
9
0
0
DPLX
8
1
8
1
0
shows the PHY control register.
TEST
COL
MC9S12NE64 Ethernet Physical Transceiver (EPHY)
7
0
7
0
0
SUP
PRE
6
0
6
0
0
EPHY Registers and Configuration
COMP
AN
5
0
0
5
0
REM
FLT
Interrupt Control Register
4
0
0
4
0
ABL
AN
3
0
3
0
0
STST
LNK
2
0
0
2
0
JAB
DT
1
0
1
0
0
CAP
EX
0
0
0
0
0
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