AN2692 Freescale Semiconductor / Motorola, AN2692 Datasheet - Page 17

• Manufacturer Part Number: AN2692
• Description: MC9S12NE64 Integrated Ethernet Controller
• Manufacturer: Freescale Semiconductor / Motorola

EMAC Enable (EMACE)
Setting the EMAC enable (EMACE) bit in the NETCTL register enables the EMAC. Before enabling the
EMAC, it is important to configure several other EMAC options. Some of these EMAC options are write-
once before the EMAC is enabled; others should be changed only while the EMAC is disabled.
Full Duplex (FDX)
The full duplex (FDX) bit in the NETCTL register configures the EMAC duplex setting. The EMAC can be
configured in half-duplex (FDX = 0) or full-duplex (FDX = 1) mode. The duplex setting in the EMAC must
be equivalent to the duplex setting in the PHY. If the PHY uses auto-negotiation, the duplex setting of the
PHY can be determined when a link is established and auto-negotiation is complete
In half-duplex mode, the carrier sense multiple access/collision detect (CSMA/CD) protocol is used by the
EMAC in half-duplex. Using CSMA/CD provides a mechanism by which two or more network devices can
share a common communication medium by allowing only one device to transmit at a time. When more
than one network devices transmit simultaneously, their data collide and corrupt the transmission. In full-
duplex mode, simultaneous two-way transmissions over point-to-point links are allowed and the
CSMA/CD protocol is not required.
External PHY (EXTPHY)
The EXTPHY bit in the NETCTL register can configure the MC9S12NE64 PG[6:0], PH[6:0], and PJ[3:0]
pins to operate as an external MII. This allows the user to bypass the internal EPHY of the MC9S12NE64
device for either MII bus testing or to interface to an external PHY. If EXTPHY is set, the EPHY must not
be enabled. EXTPHY must be cleared (0) if using the MC9S12NE64 internal EPHY. If EXTPHY is cleared,
pins function as general-purpose input/output pins.
pin.
Freescale Semiconductor
Reset:
Read:
Write:
EMACE
Bit 7
0
Figure 10. Network Control (NETCTL) Register
MC9S12NE64 Integrated Ethernet Controller, Rev. 0.2
Pin MII Function
EXTPHY Bit Set
(EXTPHY = 1)
= Unimplemented
MII_RXCLK
MII_RXER
MII_RXDV
Table 1. MII Signal Descriptions
6
0
0
5
0
0
Table 1
ESWAI
Receive error
Receive data valid
Receive clock
4
0
MII Signal Description
MC9S12NE64 Ethernet Media Access Controller (EMAC)
describes the MII interface mode for each MII
EXTPHY
3
0
MLB
2
0
FDX
1
0
(Figure
Bit 0
0
0
22).
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