AN2692 Freescale Semiconductor / Motorola, AN2692 Datasheet - Page 34

• Manufacturer Part Number: AN2692
• Description: MC9S12NE64 Integrated Ethernet Controller
• Manufacturer: Freescale Semiconductor / Motorola

Initializing the MC9S12NE64 Ethernet Controller
Initializing the MC9S12NE64 Ethernet Controller
The EMAC and EPHY are designed as two separate modules on the MC9S12NE64, but if using the
internal EPHY, they should be initialized together. The following procedure will prepare the MC9S12NE64
integrated Ethernet controller for general Ethernet operation.
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10. Configure the EMAC maximum reception frame length using the MAXFL bit field in the BUFCFG
11. Configure the MAC hardware 6-byte address using the MACAD registers.
12. Configure the EMAC Ethertype filter mode using the ETYPE and ETCTL registers.
13. Configure the EMAC MAC hardware address filter mode. Options include configuring the BCREJ,
14. Configure EMAC loopback (MLB bit) and external PHY mode (EXTPHY bit) if required. If auto-
15. Enable the EMAC by setting the EMACE bit in the NETCTL register.
16. Configure and enable EMAC interrupts as needed using the EMAC interrupt mask (IMASK)
17. Initialize and transmit pause time duration:
18. Enable system interrupts.
1. Initialize the CRG to generate a 25-MHz internal bus clock. This is required for 100-Mbps
2. Disable the EPHY clock by setting the DIS10 and DIS100 bits in the EPHYCTL0 register to 1. The
3. Configure the PHY address using the EPHYCTL1 register bits EPHYADD[4:0]. EPHYADD[4:0] will
4. Configure auto-negotiation:
5. Enable EPHY LEDs by setting the LEDEN bit in the EPHYCTL0 register.
6. Enable EPHY interrupts by setting the LEDEN bit in the EPHYCTL0 register.
7. Enable EPHY by setting the EPHYEN bit in the EPHYCTL0 register. If the EPHY is enabled, MII
8. Configure the EMAC MDC clock using the MDCSEL bits in the MCMST register.
9. Configure the EMAC Ethernet buffer space in memory using the BUFMAP bit field in BUFCFG
operation. A 2.5-MHz bus clock would be acceptable for 10-Mbps operation, but remember that the
MC9S12NE64 requires a 25-MHz clock input.
EPHY clocks will not be enabled until both EMAC and EPHY are completely configured.
latch EPHY register 14 when the EPHYEN bit is set.
–
–
operation between the EMAC and EPHY is possible.
register.
register.
CONMC, and PROM bits of the RXCTS register. The receive flow control configuration (RFCE bit)
must be configured only if auto-negotiation is disabled. If auto-negotiation is used, this setting must
be configured after auto-negotiation is complete and the pause setting is resolved.
negotiation is disabled, the EMAC duplex mode (FDX bit) can also be configured. If auto-
negotiation is enabled, the EMAC duplex mode should be configured after auto-negotiation is
complete.
register.
a.
b.
If auto-negotiation is used, clear the ANDIS bit in the EPHYCTL0 register.
If auto-negotiation is not used, set the ANDIS bit in the EPHYCTL0 register.
Set the PTRC bit in the TXSCTS register.
Configure the PTIME register.
MC9S12NE64 Integrated Ethernet Controller, Rev. 0.2
Freescale Semiconductor