AN2692 Freescale Semiconductor / Motorola, AN2692 Datasheet - Page 28

no-image

AN2692

Manufacturer Part Number
AN2692
Description
MC9S12NE64 Integrated Ethernet Controller
Manufacturer
Freescale Semiconductor / Motorola
Datasheet
MC9S12NE64 Ethernet Physical Transceiver (EPHY)
EPHY Registers and Configuration Options
The integrated EPHY is designed to provide control and status access by the EMAC (through the MII
management interface). Therefore, the EPHY has only a few directly accessible registers. The EPHY
registers available from the EPHY register map include:
EPHYCTL0 and EPHYCTL1 are used mainly to enable the EPHY (by setting the EPHYCTL0 EPHYEN
bit).
28
RxN
RxP
TxP
TxN
R
Bias
Figure 20
100BASE-TX
LOOPBACK
Ethernet physical transceiver control register 0 (EPHYCTL0)
Ethernet physical transceiver control register 1 (EPHYCTL1)
Ethernet physical transceiver status register (EPHYSR)
shows the EPHYCTL0 and EPHYCTL1 registers.
100BASE-TX
10BASE-T
RECEIVER
RECEIVER
100BASETX
VOLTAGE/CURRENT
DRIVER
10BASET
DRIVER
REFERENCES
MC9S12NE64 Integrated Ethernet Controller, Rev. 0.2
10BASE-T
DIG LOOP B
Figure 19. EPHY Block Diagram
POLARITY CORRECTION
(COARSE EQUALIZER)
DIGITAL EQUALIZER
TIMING CONTROL
LINK DETECT
MLT-3 ENCODE
VGA CONTROL
BLW CONTROL
SCRAMBLER
SQUELCH
100BASE-TX
DIG LOOP B
SLICER
100BASE-TX
10BASE-T
PLL
PLL
NEGOTIATE
AUTO
MLT-3 DECODE
DESCRAMBLER
4B/5B
ENCODE
MANCHESTER ENCODER
DIGITAL WAVE SHAPING
MANCHESTER DECODE
CLOCK RECOVERY
CARRIER SENSE
COLLISION
4B/5B
DECODE
CONFIGURATION
Freescale Semiconductor
MANAGEMENT
REGISTERS
LOOPBACK
(MII)
MII
MII
CLOCK
MDIO
REF

Related parts for AN2692