LM3S101-CRN20-XNPT Luminary Micro, Inc., LM3S101-CRN20-XNPT Datasheet - Page 8

• Manufacturer Part Number: LM3S101-CRN20-XNPT
• Description: Microcontroller
• Manufacturer: Luminary Micro, Inc.

List of Registers
System Control ............................................................................................................................... 44
Register 1:
Register 2:
Register 3:
Register 4:
Register 5:
Register 6:
Register 7:
Register 8:
Register 9:
Register 10:
Register 11:
Register 12:
Register 13:
Register 14:
Register 15:
Register 16:
Register 17:
Register 18:
Register 19:
Register 20:
Register 21:
Register 22:
Register 23:
Register 24:
Register 25:
Register 26:
Register 27:
Register 28:
Register 29:
Internal Memory .............................................................................................................................. 80
Register 1:
Register 2:
Register 3:
Register 4:
Register 5:
Register 6:
Register 7:
Register 8:
Register 9:
General-Purpose Input/Outputs (GPIOs) ...................................................................................... 93
Register 1:
Register 2:
Register 3:
Register 4:
Register 5:
March 22, 2006
Device Identification 0 (DID0), offset 0x000............................................................................ 52
Device Identification 1 (DID1), offset 0x004............................................................................ 53
Device Capabilities 0 (DC0), offset 0x008 .............................................................................. 55
Device Capabilities 1 (DC1), offset 0x010 .............................................................................. 56
Device Capabilities 2 (DC2), offset 0x014 .............................................................................. 57
Device Capabilities 3 (DC3), offset 0x018 .............................................................................. 58
Device Capabilities 4 (DC4), offset 0x01C.............................................................................. 59
Power-On and Brown-Out Reset Control (PBORCTL), offset 0x030...................................... 60
LDO Power Control (LDOPCTL), offset 0x034 ....................................................................... 61
Software Reset Control 0 (SRCR0), offset 0x040................................................................... 62
Software Reset Control 1 (SRCR1), offset 0x044................................................................... 63
Software Reset Control 2 (SRCR2), offset 0x048................................................................... 64
Raw Interrupt Status (RIS), offset 0x050 ................................................................................ 65
Interrupt Mask Control (IMC), offset 0x054............................................................................. 66
Masked Interrupt Status and Clear (MISC), offset 0x058 ....................................................... 68
Reset Cause (RESC), offset 0x05C........................................................................................ 69
Run-Mode Clock Configuration (RCC), offset 0x060 .............................................................. 70
XTAL to PLL Translation (PLLCFG), offset 0x064.................................................................. 74
Run-Mode Clock Gating Control 0 (RCGC0), offset 0x100 .................................................... 75
Sleep-Mode Clock Gating Control 0 (SCGC0), offset 0x110 .................................................. 75
Deep-Sleep-Mode Clock Gating Control 0 (DCGC0), offset 0x120 ........................................ 75
Run-Mode Clock Gating Control 1 (RCGC1), offset 0x104 .................................................... 76
Sleep-Mode Clock Gating Control 1 (SCGC1), offset 0x114 .................................................. 76
Deep-Sleep-Mode Clock Gating Control 1 (DCGC1), offset 0x124 ........................................ 76
Run-Mode Clock Gating Control 2 (RCGC2), offset 0x108 .................................................... 77
Sleep-Mode Clock Gating Control 2 (SCGC2), offset 0x118 .................................................. 77
Deep-Sleep-Mode Clock Gating Control 2 (DCGC2), offset 0x128 ........................................ 77
Clock Verification Clear (CLKVCLR), offset 0x150 ................................................................. 78
Allow Unregulated LDO to Reset the Part (LDOARST), offset 0x160 .................................... 79
Flash Memory Protection Read Enable (FMPRE), offset 0x130............................................. 84
Flash Memory Protection Program Enable (FMPPE), offset 0x134........................................ 84
U Second Reload (USECRL), offset 0x140 ............................................................................ 85
Flash Memory Address (FMA), offset 0x000 .......................................................................... 86
Flash Memory Data (FMD), offset 0x004................................................................................ 87
Flash Memory Control (FMC), offset 0x008............................................................................ 88
Flash Controller Raw Interrupt Status (FCRIS), offset 0x00C ................................................ 90
Flash Controller Interrupt Mask (FCIM), offset 0x010............................................................. 91
Flash Controller Masked Interrupt Status and Clear (FCMISC), offset 0x014 ........................ 92
GPIO Data (GPIODATA), offset 0x000................................................................................. 100
GPIO Direction (GPIODIR), offset 0x400.............................................................................. 101
GPIO Interrupt Sense (GPIOIS), offset 0x404 ...................................................................... 102
GPIO Interrupt Both Edges (GPIOIBE), offset 0x408 ........................................................... 103
GPIO Interrupt Event (GPIOIEV), offset 0x40C .................................................................... 104
Preliminary
LM3S101 Data Sheet
8