LM3S101-CRN20-XNPT Luminary Micro, Inc., LM3S101-CRN20-XNPT Datasheet - Page 71

• Manufacturer Part Number: LM3S101-CRN20-XNPT
• Description: Microcontroller
• Manufacturer: Luminary Micro, Inc.

System Control
71
Bit/Field
26:23
21:14
22
13
12
11
USESYS
reserved
BYPASS
PWRDN
SYSDIV
Name
OEN
Type
R/W
R/W
R/W
R/W
R/W
RO
Reset
0xF
0
1
1
1
1
Preliminary
Description
System Clock Divisor
Specifies which divisor is used to generate the system clock
from the PLL output (200 MHz).
When reading the Run-Mode Clock Configuration (RCC)
register (see page 70), the SYSDIV value will be
MINSYSDIV if a lower divider was requested and the PLL is
being used. This lower value will be allowed to divide a non-
PLL source.
clock. The system clock divider is forced to be used when
the PLL is selected as the source.
Read as 1.
PLL Power Down
This bit connects to the PLL PWRDN input. The reset value
of 1 powers down the PLL. See Table 6-4 on page 73 for
PLL mode control.
PLL Output Enable
This bit specifies whether the PLL output driver is enabled.
If cleared, the driver transmits the PLL clock to the output.
Otherwise, the PLL clock does not oscillate outside the PLL
module.
Note:
PLL Bypass
Chooses whether the system clock is derived from the PLL
output or the OSC source. If set, the clock that drives the
system is the OSC source. Otherwise, the clock that drives
the system is the PLL output clock divided by the system
divider.
Use the system clock divider as the source for the system
Binary
Value
0000-
1000
1001
1010
1011
1100
1101
1110
1111
Both PWRDN and OEN must be cleared to run the
PLL.
Divisor
(BYPASS=1)
reserved
/10
/11
/12
/13
/14
/15
/16
Frequency
(BYPASS=0)
reserved
20 MHz
18.18 MHz
16.67 MHz
15.38 MHz
14.29 MHz
13.33 MHz
12.5 MHz
(default)
March 22, 2006