LM3S101-CRN20-XNPT Luminary Micro, Inc., LM3S101-CRN20-XNPT Datasheet - Page 138

• Manufacturer Part Number: LM3S101-CRN20-XNPT
• Description: Microcontroller
• Manufacturer: Luminary Micro, Inc.

9.3.2
9.3.3
9.3.4
March 22, 2006
32-Bit Real-Time Clock (RTC) Mode
To use the RTC mode, the timer must have a 32-KHz input signal on its 32KHz pin. To enable the
RTC feature, follow these steps:
1.
2.
3.
4.
5.
6.
When the timer count equals the value in the GPTMTAMATCHR register, the counter is re-loaded
with 0x00000000 and begins counting. If an interrupt is enabled, it does not have to be cleared.
16-Bit One-Shot/Periodic Timer Mode
A timer is configured for 16-bit One-Shot and Periodic modes by the following sequence:
1.
2.
3.
4.
5.
6.
7.
8.
In One-Shot mode, the timer stops counting after step 8. To re-enable the timer, repeat the
sequence. A timer configured in Periodic mode does not stop counting after it times out.
16-Bit Input Edge Count Mode
A timer is configured to Input Edge Count mode by the following sequence:
1.
2.
3.
4.
5.
6.
7.
Ensure the timer is disabled (the TAEN bit is cleared) before making any changes.
Write the Configuration Register (GPTMCFG) with a value of 0x1.
Write the desired match value to the TimerA Match Register (GPTMTAMATCHR).
Set/clear the RTCEN bit in the Control Register (GPTMCTL) as desired.
If interrupts are required, set the RTCIM bit in the Interrupt Mask Register (GPTMIMR).
Set the TAEN bit in the GPTMCTL register to enable the timer and start counting.
Ensure the target timer is disabled (the TnEN bit is cleared) before making any changes.
Write the Configuration Register (GPTMCFG) to a value of 0x4.
Set the TnMR field in the Timer Mode (GPTMTnMR) register:
a.
b.
If a prescaler is to be used, write the prescale value to the Timern Prescale Register
(GPTMTnPR).
Load the start value into the Timer Interval Load Register (GPTMTnILR).
If interrupts are required, set the TnTOIM bit in the Interrupt Mask Register (GPTMIMR).
Set the TnEN bit in the Control Register (GPTMCTL) to enable the timer and start counting.
Poll the TnTORIS bit in the GPTMRIS register or wait for the interrupt to be generated (if
enabled). In both cases, the status flags are cleared by writing a 1 to the TnTOCINT bit of the
Interrupt Clear Register (GPTMICR).
Ensure the timer is disabled (the TnEN bit is cleared) before making any changes.
Write the GPTM Configuration (GPTMCFG) register to a value of 0x4.
In the GPTM Timer Mode (GPTMTnMR) register, write the TnCMR field to 0x0 and the TnMR
field to 0x3.
Configure the type of event(s) that the timer will capture by writing the TnEVENT field of the
GPTM Control (GPTMCTL) register.
Load the timer start value into the Timern Interval Load (GPTMTnILR) register.
Load the desired event count into the Timern Match (GPTMTnMATCHR) register.
If interrupts are required, set the CnMIM bit in the GPTM Interrupt Mask (GPTMIMR) register.
Write a value of 0x1 for One-Shot mode.
Write a value of 0x2 for Periodic mode.
Preliminary
LM3S101 Data Sheet
138