LM3S101-CRN20-XNPT Luminary Micro, Inc., LM3S101-CRN20-XNPT Datasheet - Page 105

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LM3S101-CRN20-XNPT

Manufacturer Part Number
LM3S101-CRN20-XNPT
Description
Microcontroller
Manufacturer
Luminary Micro, Inc.
Datasheet
General-Purpose Input/Outputs (GPIOs)
105
Reset
Reset
Type
Type
GPIO Interrupt Mask (GPIOIM)
Offset 0x410
RO
RO
31
15
0
0
31:8
7:0
Bit
Register 6: GPIO Interrupt Mask (GPIOIM), offset 0x410
The GPIOIM register is the interrupt mask register. Bits set to High in GPIOIM allow the
corresponding pins to trigger their individual interrupts and the combined GPIOINTR line. Clearing
a bit disables interrupt triggering on that pin. All bits are cleared by a reset.
RO
RO
30
14
0
0
reserved
Name
IME
RO
RO
29
13
0
0
RO
RO
28
12
0
0
reserved
Type
R/W
RO
RO
RO
27
11
0
0
RO
RO
26
10
0
0
Reset
0x00
0
RO
RO
25
0
9
0
Preliminary
Description
Reserved bits return an indeterminate value, and should never
be changed.
GPIO Interrupt Mask Enable
0: Corresponding pin interrupt is masked.
1: Corresponding pin interrupt is not masked.
RO
RO
24
0
8
0
reserved
R/W
RO
23
0
7
0
R/W
RO
22
0
6
0
R/W
RO
21
0
5
0
R/W
RO
20
0
4
0
IME
R/W
RO
19
0
3
0
R/W
RO
18
0
2
0
March 22, 2006
R/W
RO
17
0
1
0
R/W
RO
16
0
0
0

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