LM3S101-CRN20-XNPT Luminary Micro, Inc., LM3S101-CRN20-XNPT Datasheet - Page 56

• Manufacturer Part Number: LM3S101-CRN20-XNPT
• Description: Microcontroller
• Manufacturer: Luminary Micro, Inc.

a. These bits mask the Run-Mode Clock Gating Control 0 (RCGC0) register (see page 113), Sleep-Mode Clock Gating Control
March 22, 2006
Reset
Reset
Type
Type
0 (SCGC0) register (see page 113), and Deep-Sleep-Mode Clock Gating Control 0 (DCGC0) register (see page 113). Bits that
are not noted are passed as 0. ADCSP is clipped to the maximum value specified in DC1.
31:16
15:12
Bit/Field
11:8
Device Capabilities 1 (DC1)
Offset 0x010
6:5
7
4
3
2
1
0
RO
RO
31
15
0
1
Register 4: Device Capabilities 1 (DC1), offset 0x010
This register is predefined by the part and can be used to verify features. It also acts as a mask for
write operations to the Run-Mode Clock Gating Control 0 (RCGC0) register (see page 75),
Sleep-Mode Clock Gating Control 0 (SCGC0) register (see page 75), and Deep-Sleep-Mode
Clock Gating Control 0 (DCGC0) register (see page 75).
MINSYSDIV
RO
RO
30
14
0
0
MINSYSDIV
reserved
reserved
reserved
JTAG
SWO
SWD
Name
WDT
MPU
PLL
RO
RO
29
13
0
0
a
a
a
a
RO
RO
28
12
0
1
Type
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
27
11
0
0
RO
RO
26
10
0
0
reserved
Reset
0x09
0x0
RO
RO
25
0
9
0
0
0
0
1
1
1
1
1
Preliminary
RO
RO
24
0
8
0
reserved
Description
Reserved bits return an indeterminate value, and should
never be changed.
The reset value is hardware-dependent. The value of 0x09
specifies a 20-MHz CPU clock with a PLL divider of 10.
Reserved bits return an indeterminate value, and should
never be changed.
This bit indicates whether the Memory Protection Unit
(MPU) in the Cortex-M3 is available. A 0 indicates the MPU
is not available; a 1 indicates the MPU is available.
See the ARM® Cortex™-M3 Technical Reference Manual
for details on the MPU.
Reserved bits return an indeterminate value, and should
never be changed.
A 1 in this field indicates the presence of an implemented
PLL in the device.
A 1 in this field indicates a watchdog timer on the device.
A 1 in this field indicates the presence of the ARM Serial
Wire Output (SWO) trace port capabilities.
A 1 in this field indicates the presence of the ARM Serial
Wire Debug (SWD) capabilities.
A 1 in this field indicates the presence of a JTAG port.
MPU
RO
RO
23
0
7
0
RO
RO
22
0
6
0
reserved
RO
RO
21
0
5
0
PLL
RO
RO
20
0
4
1
WDT
RO
RO
19
0
3
1
LM3S101 Data Sheet
SWO
RO
RO
18
0
2
1
SWD
RO
RO
17
0
1
1
JTAG
RO
RO
16
0
0
1
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