LM3S101-CRN20-XNPT Luminary Micro, Inc., LM3S101-CRN20-XNPT Datasheet - Page 153

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LM3S101-CRN20-XNPT

Manufacturer Part Number
LM3S101-CRN20-XNPT
Description
Microcontroller
Manufacturer
Luminary Micro, Inc.
Datasheet
General-Purpose Timers
153
Reset
Reset
Type
Type
GPTM TimerB Match (GPTMTBMATCHR)
Offset 0x034
31:16
R/W
RO
15
31
0
0
15:0
Bit
Register 12: GPTM TimerB Match (GPTMTBMATCHR), offset 0x034
This register is used in 32-bit Real-Time Clock mode and 16-bit PWM and Input Edge Count
modes.
R/W
RO
14
30
0
0
reserved
TBMRL
Name
R/W
RO
29
13
0
0
R/W
RO
12
28
0
0
Type
R/W
RO
R/W
RO
11
27
0
0
R/W
RO
10
26
0
0
0xFFFF
Reset
0
R/W
RO
25
0
9
0
Preliminary
Description
Reserved bits return an indeterminate value, and should never
be changed.
GPTM TimerB Match Register Low
When configured for PWM mode, this value along with
GPTMTBILR, determines the duty cycle of the output PWM
signal.
When configured for Edge Count mode, this value along with
GPTMTBILR, determines how many edge events are counted.
The total number of edge events counted is equal to the value
in GPTMTBILR minus this value.
R/W
RO
24
0
8
0
reserved
TBMRL
R/W
RO
23
7
0
0
R/W
RO
22
6
0
0
R/W
RO
21
0
5
0
R/W
RO
20
0
4
0
R/W
RO
19
3
0
0
R/W
RO
18
2
0
0
March 22, 2006
R/W
RO
17
1
0
0
R/W
RO
16
0
0
0

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