FLLXT971A Intel, FLLXT971A Datasheet - Page 74

• Manufacturer Part Number: FLLXT971A
• Description: 3.3V Dual Speed Fast Ethernet PHY Transceicer
• Manufacturer: Intel

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LXT971A 3.3V Dual-Speed Fast Ethernet Transceiver
74
Table 43. Control Register (Address 0)
1. R/W = Read/Write
2. Default value of Register bits 0.12, 0.13 and 0.8 are determined by the LED/CFG n pins (refer to
0.5:0
0.15
0.14
0.13
0.12
0.11
0.10
Bit
0.9
0.8
0.7
0.6
RO = Read Only
SC = Self Clearing
page
30).
Reset
Loopback
Speed Selection
Auto-Negotiation
Enable
Power-Down
Isolate
Restart
Auto-Negotiation
Duplex Mode
Collision Test
Speed Selection
Reserved
Name
1 = PHY reset
0 = Normal operation
1 = Enable loopback mode
0 = Disable loopback mode
1 = Enable auto-negotiation process
0 = Disable auto-negotiation process
1 = Power-down
0 = Normal operation
1 = Electrically isolate PHY from MII
0 = Normal operation
1 = Restart auto-negotiation process
0 = Normal operation
1 = Full-duplex
0 = Half-duplex
1 = Enable COL signal test
0 = Disable COL signal test
Write as 0, ignore on Read
0.6
0.6
1
1
0
0
1
1
0
0
0.13
0.13
1
0
1
0
1
0
1
0
Reserved
1000 Mbps (not supported)
100 Mbps
10 Mbps
Reserved
1000 Mbps (not supported)
100 Mbps
10 Mbps
Description
Speed Selected
Speed Selected
Rev. Date: August 7, 2002
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
SC
SC
Document #: 249414
1
Revision #: 002
Datasheet
Table 9 on
Default
Note 2
Note 2
Note 2
00000
0
0
0
0
0
0
0