FLLXT971A Intel, FLLXT971A Datasheet - Page 37

• Manufacturer Part Number: FLLXT971A
• Description: 3.3V Dual Speed Fast Ethernet PHY Transceicer
• Manufacturer: Intel

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Datasheet
Document #: 249414
Revision #: 002
Rev. Date: August 7, 2002
Figure 15. 100BASE-TX Data Path
Figure 16. 100BASE-TX Reception with No Errors
Figure 17. 100BASE-TX Reception with Invalid Symbol
As shown in
soon as the LXT971A detects the start of preamble, it transmits a Start-of-Stream Delimiter (SSD,
symbols J and K) to the network. It then encodes and transmits the rest of the packet, including the
balance of the preamble, the SFD, packet data, and CRC.
Once the packet ends, the LXT971A transmits the End-of- Stream Delimiter (ESD, symbols T and
R) and then returns to transmitting Idle symbols. 4B/5B coding is shown in
Figure 16
from the line, it asserts RX_ER as shown in
RXD<3:0>
RXD<3:0>
Standard Data Flow
Scrambler Bypass Data Flow
RX_CLK
RX_CLK
D0
D1
D2
D3
S0
S1
S2
S3
S4
RX_DV
RX_ER
RX_DV
RX_ER
shows normal reception with no errors. When the LXT971A receives invalid symbols
Parallel
Parallel
Parallel
Parallel
Figure 14 on page
Serial
Serial
Serial
Serial
to
to
to
to
preamble SFD SFD DA
preamble SFD SFD DA
D0 D1 D2 D3
36, the MAC starts each transmission with a preamble pattern. As
LXT971A 3.3V Dual-Speed Fast Ethernet Transceiver
4B/5B
DA
DA
DA
Figure
S0 S1 S2 S3 S4
S0 S1 S2 S3 S4
XX
DA
XX
17.
CRC
XX
XX
CRC
XX
Scramble
Scramble
De-
XX
CRC
XX
MLT3
MLT3
Table 11 on page
XX
pattern: 0, +1, 0, -1, 0, +1...
pattern: 0, +1, 0, -1, 0, +1...
All transitions must follow
All transitions must follow
0
0
CRC
No Transition = 0.
No Transition = 0.
XX
Transition = 1.
Transition = 1.
+1
+1
XX
0
0
-1
-1
0
0
40.
37