FLLXT971A Intel, FLLXT971A Datasheet - Page 63

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FLLXT971A

Manufacturer Part Number
FLLXT971A
Description
3.3V Dual Speed Fast Ethernet PHY Transceicer
Manufacturer
Intel
Datasheet

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4
Datasheet
Document #: 249414
Revision #: 002
Rev. Date: August 7, 2002
Figure 30. 100BASE-FX Receive Timing
Table 31. 100BASE-FX Receive Timing Parameters
RXD<3:0>, RX_DV, RX_ER setup
to RX_CLK High
RXD<3:0>, RX_DV, RX_ER hold
from RX_CLK High
CRS asserted to RXD<3:0>, RX_DV
Receive start of “J” to CRS asserted
Receive start of “T” to CRS de-asserted
Receive start of “J” to COL asserted
Receive start of “T” to COL de-asserted
1. Typical values are at 25 °C and are for design aid only; not guaranteed and not subject to production
2. BT is the duration of one bit as transferred to and from the MAC and is the reciprocal of the bit rate.
testing.
100BASE-T bit time = 10
RXD<3:0>
Parameter
RX_CLK
RX_DV
TPFI
CRS
COL
-8
s or 10 ns.
0ns
LXT971A 3.3V Dual-Speed Fast Ethernet Transceiver
Sym
t4
t5
t6
t7
t1
t2
t3
t4
t6
Min
10
10
12
16
10
14
3
Typ
t3
1
Max
250ns
16
22
15
18
5
t5
t7
t1
Units
BT
BT
BT
BT
BT
ns
ns
t2
2
Test Conditions
63

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