FLLXT971A Intel, FLLXT971A Datasheet - Page 38

• Manufacturer Part Number: FLLXT971A
• Description: 3.3V Dual Speed Fast Ethernet PHY Transceicer
• Manufacturer: Intel

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LXT971A 3.3V Dual-Speed Fast Ethernet Transceiver
3.7.2
3.7.3
3.7.3.1
38
Figure 18. 100BASE-TX Transmission with No Errors
Figure 19. 100BASE-TX Transmission with Collision
Collision Indication
Figure 18
and remains asserted for the duration of the collision as shown in
100BASE-X Protocol Sublayer Operations
With respect to the 7-layer communications model, the LXT971A is a Physical Layer 1 (PHY)
device. The LXT971A implements the Physical Coding Sublayer (PCS), Physical Medium
Attachment (PMA), and Physical Medium Dependent (PMD) sublayers of the reference model
defined by the IEEE 802.3u standard. The following paragraphs discuss LXT971A operation from
the reference model point of view.
PCS Sublayer
The Physical Coding Sublayer (PCS) provides the MII interface, as well as the 4B/5B encoding/
decoding function.
For 100BASE-TX and 100FX operation, the PCS layer provides IDLE symbols to the PMD-layer
line driver as long as TX_EN is de-asserted.
3.7.3.1.1 Preamble Handling
When the MAC asserts TX_EN, the PCS substitutes a /J/K symbol pair, also known as the Start-of-
Stream Delimiter (SSD), for the first two nibbles received across the MII. The PCS layer continues
to encode the remaining MII data, following the coding in
then returns to supplying IDLE symbols to the line driver.
TXD<3:0>
TXD<3:0>
TX_CLK
TX_CLK
TX_EN
TX_EN
CRS
COL
CRS
COL
shows normal transmission. Upon detection of a collision, the COL output is asserted
P
P
R
R
E
E
A
A
M
M
B
B
L
L
E
E
DA DA DA DA DA
JAM
Table
JAM
11, until TX_EN is de-asserted. It
Figure
JAM
DA
19.
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Rev. Date: August 7, 2002
JAM
DA
Document #: 249414
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Revision #: 002
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