FLLXT971A Intel, FLLXT971A Datasheet - Page 17

• Manufacturer Part Number: FLLXT971A
• Description: 3.3V Dual Speed Fast Ethernet PHY Transceicer
• Manufacturer: Intel

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Datasheet
Document #: 249414
Revision #: 002
Rev. Date: August 7, 2002
Table 2.
Table 3.
LXT971A MII Signal Descriptions (Continued)
LXT971A Network Interface Signal Descriptions
PBGA
1. Type Column Coding: I = Input, O = Output, A = Analog, OD = Open Drain
1. Type Column Coding: I = Input, O = Output, A = Analog, OD = Open Drain
2. For standard digital loopback testing (Register bit 0.14) in FX mode, the SD pin should be tied to an
PBGA
Pin#
Pin#
D3
E7
D8
A1
H2
H3
H4
H5
G2
LVPECL logic High (2.4 V).
LQFP
Pin#
LQFP
43
42
64
Pin#
3
19
20
23
24
26
MDDIS
MDC
MDIO
MDINT
TPFOP
TPFON
TPFIP
TPFIN
SD/TP
Symbol
Symbol
Type
Type
OD
I/O
O
I
I
I
I
1
1
LXT971A 3.3V Dual-Speed Fast Ethernet Transceiver
MII Control Interface Pins
Twisted-Pair/Fiber Outputs, Positive & Negative.
During 100BASE-TX or 10BASE-T operation, TPFOP/N pins drive
802.3 compliant pulses onto the line.
During 100BASE-FX operation, TPFOP/N pins produce differential
LVPECL outputs for fiber transceivers.
Twisted-Pair/Fiber Inputs, Positive & Negative.
During 100BASE-TX or 10BASE-T operation, TPFIP/N pins receive
differential 100BASE-TX or 10BASE-T signals from the line.
During 100BASE-FX operation, TPFIP/N pins receive differential
LVPECL inputs from fiber transceivers.
Signal Detect
device.
Reset and Power-Up. Media mode selection:
Tie High for FX mode (Register bit 16.0 = 1)
Tie Low for TP mode (Register bit 16.0 = 0)
Normal Operation (FX Mode): SD input from the fiber transceiver.
Normal Operation (TP Mode): Tie to GND (uses an internal pull-
down).
Management Disable. When MDDIS is High, the MDIO is disabled
from read and write operations.
When MDDIS is Low at power-up or reset, the Hardware Control
Interface pins control only the initial or “default” values of their
respective register bits. After the power-up/reset cycle is complete,
bit control reverts to the MDIO serial channel.
Management Data Clock. Clock for the MDIO serial data channel.
Maximum frequency is 8 MHz.
Management Data Input/Output. Bidirectional serial data channel
for PHY/STA communication.
Management Data Interrupt. When Register bit 18.1 = 1, an active
Low output on this pin indicates status change. Interrupt is cleared
by reading Register 19.
2
: Dual function input depending on the state of the
Signal Description
Signal Description
17