FLLXT971A Intel, FLLXT971A Datasheet - Page 40

• Manufacturer Part Number: FLLXT971A
• Description: 3.3V Dual Speed Fast Ethernet PHY Transceicer
• Manufacturer: Intel

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LXT971A 3.3V Dual-Speed Fast Ethernet Transceiver
40
Table 11. 4B/5B Coding
1. The /I/ (Idle) code group is sent continuously between frames.
2. The /J/ and /K/ (SSD) code groups are always sent in pairs; /K/ follows /J/.
3. The /T/ and /R/ (ESD) code groups are always sent in pairs; /R/ follows /T/.
4. An /H/ (Error) code group is used to signal an error condition.
Code Type
CONTROL
DATA
IDLE
undefined
undefined
undefined
4B Code
3 2 1 0
0 0 0 0
0 0 0 1
0 0 1 0
0 0 1 1
0 1 0 0
0 1 0 1
0 1 1 0
0 1 1 1
1 0 0 0
1 0 0 1
1 0 1 0
1 0 1 1
1 1 0 0
1 1 0 1
1 1 1 0
1 1 1 1
0 1 0 1
0 1 0 1
Name
K
R
J
T
I
A
B
C
D
E
0
1
2
3
4
5
6
7
8
9
F
1
2
2
3
3
5B Code
4 3 2 1 0
1 1 1 1 0
0 1 0 0 1
1 0 1 0 0
1 0 1 0 1
0 1 0 1 0
0 1 0 1 1
0 1 1 1 0
0 1 1 1 1
1 0 0 1 0
1 0 0 1 1
1 0 1 1 0
1 0 1 1 1
1 1 0 1 0
1 1 0 1 1
1 1 1 0 0
1 1 1 0 1
1 1 0 0 0
1 0 0 0 1
0 1 1 0 1
0 0 1 1 1
1 1 1 11
Used as inter-stream fill code
Start-of-Stream Delimiter (SSD),
part 1 of 2
Start-of-Stream Delimiter (SSD),
part 2 of 2
End-of-Stream Delimiter (ESD),
part 1 of 2
End-of-Stream Delimiter (ESD),
part 2 of 2
Interpretation
Data A
Data B
Data C
Data D
Data E
Data F
Data 0
Data 1
Data 2
Data 3
Data 4
Data 5
Data 6
Data 7
Data 8
Data 9
Rev. Date: August 7, 2002
Document #: 249414
Revision #: 002
Datasheet