FLLXT971A Intel, FLLXT971A Datasheet - Page 71

• Manufacturer Part Number: FLLXT971A
• Description: 3.3V Dual Speed Fast Ethernet PHY Transceicer
• Manufacturer: Intel

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Datasheet
Document #: 249414
Revision #: 002
Rev. Date: August 7, 2002
Table 41. Register Set
Register Definitions
The LXT971A register set includes multiple 16-bit registers.
listing.
individual register definitions.
Base registers (0 through 8) are defined in accordance with the “Reconciliation Sublayer and
Media Independent Interface” and “Physical Layer Link Signaling for 10/100 Mbps Auto-
Negotiation” sections of the IEEE 802.3 standard.
Additional registers are defined in accordance with the IEEE 802.3 standard for adding unique chip
functions.
Address
21-25
27-29
10
15
16
17
18
19
20
26
30
0
1
2
3
4
5
6
7
8
9
Table 42
Control Register
Status Register #1
PHY Identification Register 1
PHY Identification Register 2
Auto-Negotiation Advertisement Register
Auto-Negotiation Link Partner Base Page Ability Register
Auto-Negotiation Expansion Register
Auto-Negotiation Next Page Transmit Register
Auto-Negotiation Link Partner Received Next Page Register
1000BASE-T/100BASE-T2 Control Register
1000BASE-T/100BASE-T2 Status Register
Extended Status Register
Port Configuration Register
Status Register #2
Interrupt Enable Register
Interrupt Status Register
LED Configuration Register
Reserved
Digital Config Register
Reserved
Transmit Control Register
is a complete memory map of all registers and
Register Name
LXT971A 3.3V Dual-Speed Fast Ethernet Transceiver
Table 41
Tables 43 through 58
Refer to
Refer to
Refer to
Refer to
Refer to
Refer to
Refer to
Refer to
Refer to
Not Implemented
Not Implemented
Not Implemented
Refer to
Refer to
Refer to
Refer to
Refer to
–
Refer to
–
Refer to
presents a complete register
Bit Assignments
Table 43 on page 74
Table 44 on page 75
Table 45 on page 76
Table 46 on page 76
Table 47 on page 77
Table 48 on page 78
Table 49 on page 79
Table 50 on page 79
Table 51 on page 80
Table 52 on page 81
Table 53 on page 82
Table 54 on page 83
Table 55 on page 84
Table 56 on page 85
Table 57 on page 86
Table 58 on page 87
provide
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