IDT88P8344 Integrated Device Technology, IDT88P8344 Datasheet - Page 84

• Manufacturer Part Number: IDT88P8344
• Description: Spi Exchange 4 X Spi-3 To Spi-4 Issue 1.0
• Manufacturer: Integrated Device Technology

11.6.3 SPI-4 LVTTL Status AC characteristics
NOTE:
1. For the SPI-4 LVTTL valid, hold & setup the edge is configurable. The SPI-4 ingress LVTTL status clock active edge is
configured by I_CLK_EDGE field in Table 89-SPI-4 Ingress Configuration Register on page 69. The SPI-4 egress LVTTL
status clock active edge is configured by E_CLK_EDGE field in Table 104-SPI-4 Egress Configuration Register on page 73.
11.6.4 REF_CLK clock input
11.6.5 MCLK internal clock and OCLK[3:0] clock outputs
11.6.6 Microprocessor interface
IDT88P8344 SPI EXCHANGE 4 x SPI-3 TO SPI-4
Inputs
Duty cycle
Frequency (DDR)
Frequency (DDR)
TR, TF
Deskew
Outputs
Duty cycle
Frequency (DDR)
Frequency (DDR)
TR, TF
Tskew
SYNTH Jitter
TD
SPI-4 LVTTL Status
STAT_T[1:0] to SCLK_T setup time
SCLK_T to STAT_T [1:0] hold time
SCLK_T to STAT_T [1:0] delay
REF_CLK
Duty cycle
F
T
OCLK[3:0]
Duty cycle
Frequency
Output skew
between OCLKs
T
MCLK
Frequency
All outputs
T
All inputs
T
R
R
R
R
REF_CLK
, T
, T
, Tf
, T
F
F
F
Parameter
MHz
Unit
Unit
%
ns
ns
ns
MHz
MHz
Unit
%
ns
(1)
MHz
MHz
MHz
MHz
Unit
%
ps
UI
%
ps
ps
UI
ns
Min.
12.5
Min.
30
—
Min.
45
40
80
1
Min.
200
300
200
300
19.44
45
80
—
45
80
—
—
—
Typ.
Typ.
50
—
Typ.
104
Symbol
50
—
T
Typ.
T
T
311
311
SU
50
50
—
—
—
—
—
—
—
—
H
D
Max.
Max.
70
25
10
10
5
Max.
133
100
55
2
Max.
+/- 1
Conditions
200
400
500
200
400
500
0.1
55
55
50
—
REF_CLK clock input duty cycle
Main reference clock input
Rise fall time ( 20%, 80% )
Description
Rise, fall time (20%, 80%)
Rise, fall time (20%,80%)
OCLK[3:0] outputs, clock duty cycle
Description
OCLK[3:0], programmable
One pll_oclk cycle of deliberate
skew between each OCLK[3:0]
OCLK[3:0] rise, fall time (20%,80%)
Programmable
Description
I_DCLK ingress clock duty cycle
Ingress clock frequency, I_LOW=1
Ingress clock frequency, I_LOW=0
Input rise or fall time ( 20%, 80% )
Bit line deskew
E_DCLK Egress clock duty cycle
Egress clock frequency, E_LOW=1
Egress clock frequency, E_LOW=0
Output rise or fall time ( 20%, 80% )
Output differential skew, P to N
PLL jitter as a fraction of the clock cycle
Adjustable
Min
0.5
2
84
Typ
1
Max
1.2
Unit
ns
ns
ns
INDUSTRIAL TEMPERATURE RANGE
APRIL 10, 2006