IDT88P8344 Integrated Device Technology, IDT88P8344 Datasheet - Page 29

• Manufacturer Part Number: IDT88P8344
• Description: Spi Exchange 4 X Spi-3 To Spi-4 Issue 1.0
• Manufacturer: Integrated Device Technology

SPI-3 ingress to SPI-4 egress flow control
that the SPI-3 physical interface port is configured in Link mode, and the case
that the SPI-3 is configured in PHY mode. Note that since the SPI-3 physical
interfaces are configured separately, the device is able to deal with the case that
some of the LP fragments have been received on a Link layer device SPI-3
interface and some have been received on a PHY layer device SPI-3 interface.
through the RENB signal. Two modes of operation are implemented and
configurable for flow control on this interface – either the data can be allowed
to flow freely into the device or the RENB signal will be asserted if a condition
arises that one of the LPs is unable to receive another fragment. The first of these
modes is considered to have no Link layer device flow control, and the second
has Link layer device flow control.
another fragment will cause an LP overflow.
of the data buffers in each of the LPs in the PHY. This knowledge is attained either
through byte level polling or packet level polling.
associated with an LP. The SPI-4 PFP is updated with the number of free
segments available to the LP. The SPI-4 PFP determines which LP to service
based on two factors: whether the LP contains enough data for a burst, and the
starving / hungry / satisfied state of the LP. For details on the mapping of LPs
to LIDs, refer to Table 101 - SPI-4 egress LID to LP Map Block_base 0x0400
= Register_offset 0x00 - 0xFF.
through the IDT88P8344 device.
IDT88P8344 SPI EXCHANGE 4 x SPI-3 TO SPI-4
For control information there are two separate cases to consider: The case
For a device in Link mode the Link device can only control the flow of data
For the no Link flow control mode, any data sent to an LP unable to receive
For a device in Link mode the Link has complete knowledge of the fill level
Both in Link and PHY modes, the data is collected to buffer segments
The diagram below shows the SPI-3 ingress to SPI-4 egress flow control Path
DATA PATH
Min: 19.44MHz
Max: 133MHz
8 bit / 32 bit
4 x SPI-3
STATUS
Figure 17. SPI-3 ingress to SPI-4 egress flow control path
JTAG
LID Counters Memory
uproc
SPI-3 /
LID map
Memory
Main
29
A
SPI-3 ingress flow control registers
instantiations per device.
Backpressure enable
accept data
leading to fragments being discarded.
SPI-4 egress flow control configurable parameters
SPI-4 egress flow control calendar and shadow calendar
SPI-4 egress flow control multiple burst enable
to increase throughput in systems with long latency between updates.
The following are implemented per SPI-3 interface, and there are four
Link mode only
Enables the assertion of the I_ENB pin when at least one active LID can not
If not enabled, the I_ENB signal will never be asserted in Link mode, possibly
All parameters as listed in SPI-4 implementation agreement:
CALENDAR_LEN: 4 to 1,024 in increments of 4
CALENDAR_M: 1 to 256 in increments of 1
MaxBurst1 (MaxBurst_S): 16 to 256 in increments of 16
MaxBurst2 (MaxBurst_H): 16 to 256 in increments of 16
Alpha: 1 to 256 in increments of 1
DATA_MAX_T: 1 to 4,294,967,040 in increments of 1
FIFO_MAX_T: 1 to 16,777,215 in increments of 1
256 entries
Allows more than one burst to be sent to an LP. This feature was included
Chip Counters Memory
STATUS
SPI-4 /
LID map
6370 drw12a
INDUSTRIAL TEMPERATURE RANGE
Max:400 MHz
Min: 80 MHz
SPI-4.2
STATUS
APRIL 10, 2006
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