IDT88P8344 Integrated Device Technology, IDT88P8344 Datasheet - Page 43

• Manufacturer Part Number: IDT88P8344
• Description: Spi Exchange 4 X Spi-3 To Spi-4 Issue 1.0
• Manufacturer: Integrated Device Technology

8.2.5 SPI-4 status channel software
loading the appropriate status channel binary file to activate the firmware.
Download LVTTL.bin when using LVTTL status mode. Download LVDS.bin
when using LVDS status mode. This step should be performed as the third step
in the chip configuration sequence after reset in section 8.2.1.
8.2.6 IDT88P8344 layout guidelines
SPI-3 LAYOUT GUIDELINES
end length. Place the series resistor as close as possible to the driver, but no
more than 1/2 inch away from the driving end. SPI-3 inputs must have ringing
controlled to prevent the SPI-3 inputs from going more than 0.5 Volts below
ground. Use the IBIS models for more accurate results with the specific devices
being used.
T
IDT88P8344 SPI EXCHANGE 4 x SPI-3 TO SPI-4
SPI-3Clock
SPI-3Clock
D-MAX
104 MHz
104 MHz
The SPI-4 status channel may be configured to either LVTTL or LVDS by
The download process is described.
Open LVTTL.bin or LVDS.bin file
number = file length
1) Series terminate SPI-3 traces that are greater than 1/2 inch in end-to-
2) Minimize all SPI-3 data and control trace lengths to not exceed the
Direct write (0x20, 0x01); /* Write register 0x20 with 0x01 to reset */
Delay at least 5ms
ind_write(0x00c8, 0xdcb0);
- T
Direct write (0x36, 0x07);
for ( i = 0; i < number; i ++ )
Direct write (0x36, 0x00);
addr = 0x0e00;
close file
ind_write(0x00c8, 0xc860);
else
ind_write(0x00c6, 0x0e00);
{
}
SETUP
if ( number % 2 == 0 )
number = number/2 + 1;
data = (ch[1] << 8) | ch[0];
number /=2;
scr_fp.Read(ch, 2);
ind_write(addr, data);
addr ++;
addr ++;
requirement. For example, if the SPI-3 clock is 104 MHz, T
Tsetup
Tsetup
1 ns
1 ns
0.65 ns
0.65 ns
Thold Td, minimum Td, maximum Unit Interval Maximum data Maximum data Maximum Maximum Clock
Thold Td, minimum Td, maximum
2.33 ns
2.33 ns
5.65 ns
5.65 ns
clock trace
4 inches
Egress
9.6 ns
D-
43
clock trace data trace
MAX
PCB trace delay Table 18 permitted is 3 ns (Unit Interval - T
translates to a maximum PCB trace length for data and control lanes of 13.5
inches, if the loaded PCB trace delay is 220 picoseconds per inch. This is for
zero T
Clock driver or clock trace skew could reduce the T
example, if T
is 0.5 ns, the worst case PCB clock trace skew for zero T
in this example as the maximum PCB trace delay that the SPI-3 ingress clock
of the attached device can exceed the trace delay of the SPI-3 egress clock
of the device and still meet the T
zero margin, assuming the fastest device [T
the attached device and no trace delay on the data and control lanes) is 1.7
ns (Table 15 (T
7.6 inches. Trace delay on the data and control lanes would improve the T
margin in this example. This example does not include any margin for SPI-3
clock buffer skew.
and other SPI-3 clock nets of the same frequency to minimize simultaneous
switching noise. The IDT88P8344 OCLK[3:0] outputs have skew between
each output already built in, and so are useful in lowering simultaneous
switching noise. A SPI-3 clock net is defined to be the SPI-3 egress clock for
a device and the SPI-3 ingress clock for the attached device.
referencing ground planes). For example, 8 mil wide 1/2 oz copper traces
sandwiched between ground planes with 10 mil dielectric spacing between
ground planes and signal planes yields 52 Ohms single-ended, using FR-4
with a relative dielectric constant (
between adjacent SPI-3 series terminated signals is 20 mils in this example,
crosstalk between adjacent signals can be kept to 2%. Use a field solver for
more accurate results.
example trace lengths to achieve timing margin Table 16, Margin check for SPI-
3 timing, are shown. These timing budget tables do not include clock driver
relative skew incurred if different drivers are used for a SPI-3 egress and its
attached SP-3 ingress. These tables are based on timing only and do not
include such effects as crosstalk and rise time degradation.
SPI-4 LAYOUT GUIDELINES
within 100 mils or less.
within 1/2 unit interval (DDR), or less, of each other (1/4 clock period). For
8 inches
Ingress
trace delay
3) Match all SPI-3 clock lengths to within the T
4) Ensure a few nanoseconds of clock delay between one SPI-3 clock net
5) Route all SPI-3 traces as 50 Ohm embedded stripline (inner layer
An example timing budget Table 15, Zero Margin SPI-3 Timing budget, and
1) Match the P and N trace lengths within an LVDS differential signal pair to
2) Match the group of all differential data, control, and clock signal lengths to
of a device is 5.65 ns, and T
3 ns
SETUP
margin, and does not include any margin for clock driver skew.
6 inches
D-MIN
Longest
D-MIN
for the device is 1.5 ns, and T
trace length
- T
13.5 in
HOLD
data trace
Shortest
4 inches
)), for a maximum PCB clock trace difference of
SETUP
HOLD
INDUSTRIAL TEMPERATURE RANGE
of the attached device is 1 ns, the maximum
clock skew trace length
R
requirement of the attached device with
or D
1.7 ns
2.33 ns
Tsetup
margin
K
) of 4.2. If the edge to edge spacing
D-MIN
] and the worst case T
D-MIN
HOLD
SETUP
7.6 in
1.48 ns
margin
- T
for the attached device
Thold
margin in this example.
HOLD
HOLD
APRIL 10, 2006
D-MAX
requirement. For
margin (defined
- T
SETUP
HOLD
). This
HOLD
for