IDT88P8344 Integrated Device Technology, IDT88P8344 Datasheet - Page 28

• Manufacturer Part Number: IDT88P8344
• Description: Spi Exchange 4 X Spi-3 To Spi-4 Issue 1.0
• Manufacturer: Integrated Device Technology

SPI-4 egress interface port associated control
4 egress LID to LP Map Block_base 0x0400 = Register_offset 0x00 - 0xFF)
for the purpose of directing the packet fragments from the selected SPI-3 ingress
main memory buffer segment pool to the SPI-4 egress interface. The SPI-4 LID
map has 256 entries, one per LID. The SPI-4 interface has an enable bit. The
burst length is associated with the SPI-4 interface. The allowed burst range is
16 to 256 bytes per burst. The last burst of a packet can be shorter than the
programmed burst size.
ingress interface to the SPI-4 egress interface.
IDT88P8344 SPI EXCHANGE 4 x SPI-3 TO SPI-4
The SPI-4 interface has an associated LID to LP map (See Table 101 - SPI-
The diagram below shows the datapath through the device from a SPI-3
Min: 19.44MHz
Max: 133MHz
8 bit / 32 bit
4 x SPI-3
LP: Logical Port
EN: LP Enable
[LID] = LP | EN
Figure 16. SPI-3 ingress to SPI-4 egress datapath
JTAG
LID Counters Memory
Figure 15. SPI-4 egress LID to LP map
uproc
SPI-3 /
LID map
Memory
Main
A
LP
28
SPI-4 egress LID associated control
- SPI-4 egress LID to LP Map (256 entries)) is used to control the pulling of bursts
out of the buffer segment pool and into the SPI-4 egress interface. Each LID can
be enabled and disabled independently.
Chip Counters Memory
Each of the 256 entries in the SPI-4 egress LID to LP map (See Table 101
SPI-4 /
LID map
EN
6370 drw12
256 LIDs
6370 drwXD
INDUSTRIAL TEMPERATURE RANGE
Max:400 MHz
Min: 80 MHz
SPI-4.2
APRIL 10, 2006