IDT88P8344 Integrated Device Technology, IDT88P8344 Datasheet - Page 39

• Manufacturer Part Number: IDT88P8344
• Description: Spi Exchange 4 X Spi-3 To Spi-4 Issue 1.0
• Manufacturer: Integrated Device Technology

the REF_CLK input pin. The clock so selected is used for core functions of the
device, and must be present during reset and thereafter. The selection and
frequency divisors are defined by CK_SEL[3:0] pins as defined in the following
Table 14, CK_SEL[3:0] input pin encoding.
MCLK for internal use, and SPI-4 data and FIFO status channel egress clocks.
The OCLK[3:0] clock frequencies can be selected independently of each other.
OCLK[3:0] outputs always have a relative output skew of one pll_oclk (refer to
Figure 30 Clock generator) to prevent simultaneous switching when used as
SPI-3 clock sources. Use of the OCLK[3:0] outputs is encouraged for the SPI-
3 clock inputs to reduce system jitter. The frequency is divided according to the
value selected in the clock generator control register shown below. The
IDT88P8344 SPI EXCHANGE 4 x SPI-3 TO SPI-4
The device generates clocks from the SPI-4 ingress clock (I_DCLK) or from
The clock generator provides four clock outputs on the OCLK[3:0] pins,
CK_SEL[1:0]
CK_SEL[3:2]
00
01
10
11
00
01
10
11
(12.5-25 MHz)
(80-400 MHz)
REF_CLK
I_DCLK
CK_SEL[1:0]
CK_SEL[3:2]
Function
pll_rclk = REF_CLK
pll_rclk = I_DCLK/16
pll_rclk = I_DCLK /8
pll_rclk = I_DCLK /4
Function
E_DCLK = pll_oclk/2
E_DCLK = pll_oclk/4
E_DCLK = pll_oclk/6
E_DCLK = pll_oclk/8
4/8/16
MUX
Figure 30. Clock generator
(12.5-25 MHz)
(40-133 MHz)
pll_rclk
39
OCLK[3:0] pins are separately enabled by setting each associated enable flag
in Table 121, Clock generator control register (Register_offset 0x10). When an
OCLK[3:0] output is not enabled, it is in a logic low state. MCLK is the internal
processing clock, and is always enabled. Divide options should be selected to
keep the internal PLL output pll_oclk within its operating frequency range of 400
to 800 MHZ. Refer to Table 122, OCLK and MCLK frequency select encoding
for selecting the frequencies of MCLK and OCLKs. Note that divider values
should be chosen so that OCLK[3:0] and MCLK are within their specified
operating range provided in Table 136, OCLK[3:0] clock outputs and MCLK
internal clock .
low. Immediately following reset, all OCLK[3:0] outputs are active with the output
frequency defined by pll_oclk divided by the initial value in the Table 121, Clock
generator control register (Register_offset 0x10).
(400-800 MHz)
During either a hardware or a software reset, the OCLK[3:0] pins are all logic
X 32 PLL
pll_oclk
2/4/6/8
INDUSTRIAL TEMPERATURE RANGE
4
(80-400 MHz)
I_SCLK_L
E_DCLK
I_SCLK_T
6370 drw21
APRIL 10, 2006